Renesas H8S/2111B - Manual (Page 419)

Rev. 1.00, 05/04, page 385 of 544
R/W
Bit Bit Name
Initial
Value Slave Host Description
3 C/D3 0 R R Command/Data
When the host processor writes to an IDR register, bit 2
of the I/O address is written into this bit to indicate
whether IDR contains data or a command.
0: Contents of data register (IDR) are data
1: Contents of data register (IDR) are a command
2 DBU32 0 R/W R Defined by User
The user can use this bit as necessary.
1 IBF3A 0 R R Input Buffer Full
Set to 1 when the host processor writes to IDR. This bit
is an internal interrupt source to the slave processor (this
LSI). IBF is cleared to 0 when the slave processor reads
IDR.
The IBF1 flag setting and clearing conditions are
different when the fast A20 gate is used. For details see
table 15.3.
0: [Clearing condition]
When the slave processor reads IDR
1: [Setting condition]
When the host processor writes to IDR using I/O
write cycle
0 OBF3A 0 R/(W)* R Output Buffer Full
Set to 1 when the slave processor (this LSI) writes to
ODR. OBF3A is cleared to 0 when the host processor
reads ODR.
0: [Clearing condition]
When the host processor reads ODR using I/O read
cycle, or the slave processor writes 0 to the OBF bit
1: [Setting condition]
When the slave processor writes to ODR
Note: * Only 0 can be written to clear the flag.