Renesas H8S/2111B - Manual (Page 243)

Rev. 1.00, 05/04, page 209 of 544
10.5.5 TCNT External Reset Timing
TCNT is cleared at the rising edge of an external reset input, depending on the settings of the
CCLR1 and CCLR0 bits in TCR. The width of the clearing pulse must be at least 1.5 states. Figure
10.10 shows the timing of clearing the counter by an external reset input.
φ
Clear signal
External reset
input pin
TCNT N H'00 N – 1
Figure 10.10 Timing of Counter Clear by External Reset Input
10.5.6 Timing of Overflow Flag (OVF) Setting
The OVF bit in TCSR is set to 1 when the TCNT overflows (changes from H'FF to H'00). Figure
10.11 shows the timing of OVF flag setting.
φ
OVF
Overflow signal
TCNT H'FF H'00
Figure 10.11 Timing of OVF Flag Setting