Renesas H8S/2111B - Manual (Page 259)

Rev. 1.00, 05/04, page 225 of 544
Bit Bit Name
Initial
Value R/W Description
2
1
0
CKS2
CKS1
CKS0
0
0
0
R/W
R/W
R/W
Clock Select 2 to 0
Selects the clock source to be input to. The overflow
frequency for
φ = 10 MHz is enclosed in parentheses.
000:
φ/2 (frequency: 51.2 µs)
001:
φ/64 (frequency: 1.64 ms)
010:
φ/128 (frequency: 3.28 ms)
011:
φ/512 (frequency: 13.1 ms)
100:
φ/2048 (frequency: 52.4 ms)
101:
φ/8192 (frequency: 209.7 ms)
110:
φ/32768 (frequency: 0.84 s)
111:
φ/131072 (frequency: 3.36 s)
Notes: 1. Only 0 can be written, to clear the flag.
2. When OVF is polled with the interval timer interrupt disabled, OVF = 1 must be read at
least twice.
• TCSR_1
Bit Bit Name
Initial
Value R/W Description
7 OVF 0 R/(W)* 1 Overflow Flag
Indicates that TCNT has overflowed (changes from H'FF
to H'00).
[Setting condition]
When TCNT overflows (changes from H'FF to H'00)
However, when internal reset request generation is
selected in watchdog timer mode, OVF is cleared
automatically by the internal reset.
[Clearing conditions]
When TCSR is read when OVF = 1* 2 , then 0 is written to
OVF
When 0 is written to TME
6 WT/
IT
0 R/W Timer Mode Select
Selects whether the WDT is used as a watchdog timer
or interval timer.
0: Interval timer mode
1: Watchdog timer mode
5 TME 0 R/W Timer Enable
When this bit is set to 1, TCNT starts counting.
When this bit is cleared, TCNT stops counting and is
initialized to H'00.