Renesas H8S/2111B - Manual (Page 219)

Rev. 1.00, 05/04, page 185 of 544
Figures 10.1 to 10.3 show block diagrams of 8-bit timers.
External clock
sources Internal clock
sources
TMR_0
φ/2, φ/8, φ/32, φ/64, φ/256, φ/1024
Clock 1
Clock 0
Compare-match A1
Compare-match A0
Clear 1
Interrupt signals
CMIA0
CMIB0
OVI0
CMIA1
CMIB1
OVI1
TMO0
TMRI0
Internal bus
TCORA_0
Comparator A_0
Comparator B_0
TCORB_0
TCSR_0
TCR_0
TMCI0
TMCI1
TCNT_0
Overflow 1
Overflow 0
Compare-match B1
Compare-match B0
TMO1
TMRI1
Clock select
Control logic
Clear 0
TMR_1
φ/2, φ/8, φ/64, φ/128, φ/1024, φ/2048
[Legend]
TCORA_0:
TCORB_0:
TCNT_0:
TCSR_0:
TCR_0: Time constant register A_0
Time constant register B_0
Timer counter_0
Timer control/status register_0
Timer control register_0 TCORA_1:
TCORB_1:
TCNT_1:
TCSR_1:
TCR_1: Time constant register A_1
Time constant register B_1
Timer counter_1
Timer control/status register_1
Timer control register_1
TCORA_1
Comparator A_1
TCNT_1
Comparator B_1
TCORB_1
TCSR_1
TCR_1
Figure 10.1 Block Diagram of 8-Bit Timer (TMR_0 and TMR_1)