Renesas H8S/2111B - Manual (Page 266)

Rev. 1.00, 05/04, page 232 of 544
11.6.2 Conflict between Timer Counter (TCNT) Write and Increment
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write
takes priority and the timer counter is not incremented. Figure 11.7 shows this operation.
Address
φ
Internal write signal
TCNT input clock
TCNT N M
T
1
T
2
TCNT write cycle
Counter write data
Figure 11.7 Conflict between TCNT Write and Increment
11.6.3 Changing Values of CKS2 to CKS0 Bits
If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in
the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before
changing the values of bits CKS2 to CKS0.
11.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode
If the mode is switched from watchdog timer to interval timer, while the WDT is operating, errors
could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME
bit to 0) before switching the mode.