Renesas H8S/2111B - Manual (Page 509)

Rev. 1.00, 05/04, page 475 of 544
20.8 Subsleep Mode
The CPU makes a transition to subsleep mode when the SLEEP instruction is executed in
subactive mode with the SSBY bit in SBYCR cleared to 0, the LSON bit in LPWRCR set to 1,
and the PSS bit in TCSR (WDT_1) set to 1.
In subsleep mode, the CPU is stopped. Peripheral modules other than TMR_0, TMR_1, WDT_0,
and WDT_1 are also stopped. The contents of the CPU's internal registers, several on-chip
peripheral module registers, and on-chip RAM data are retained and the I/O ports retain their
values before transition as long as the prescribed voltage is supplied.
Subsleep mode is exited by an interrupt (interrupts by on-chip peripheral modules, NMI, IRQ0 to
IRQ7), the
RES pin input, or the STBY pin input.
When an interrupt occurs, subsleep mode is exited and interrupt exception handling starts.
In the case of an IRQ0 to IRQ7 interrupt, subsleep mode is not exited if the corresponding enable
bit has been cleared to 0. In the case of interrupts from the on-chip peripheral modules, subsleep
mode is not exited if the interrupt enable register has been set to disable the reception of that
interrupt, or the interrupt is masked by the CPU.
When the
RES pin is driven low, system clock oscillation starts. Simultaneously with the start of
system clock oscillation, the system clock is supplied to the entire LSI. Note that the
RES pin must
be held low until clock oscillation is stabilized. If the
RES pin is driven high after the clock
oscillation stabilization time has passed, the CPU begins reset exception handling.
If the
STBY pin is driven low, the LSI enters hardware standby mode.