Avago Technologies MegaRAID Fast Path Software - Manual (Page 17)

LSI Corporation Confidential | July 2011 Page 17
MegaRAID SAS Software User Guide Chapter 1: Overview | Configuration Scenarios
Figure 1 shows a direct-connect configuration. The Inter-IC (I
2
C) interface
communicates with peripherals. The external memory bus provides a 32-bit memory
bus, parity checking, and chip select signals for pipelined synchronous burst static
random access memory (PSBRAM), nonvolatile static random access memory
(NVSRAM), and Flash ROM.
NOTE: The external memory bus is 32-bit for the SAS 8704ELP and the SAS 8708ELP,
and 64-bit for the SAS 8708EM2, the SAS 8880EM2, and the SAS 8888ELP.
Figure 1: Example of an LSI SAS Direct-Connect Application
Figure 2 shows an example of a SAS RAID controller configured with an LSISASx12
expander that is connected to SAS disks, SATA II disks, or both.
Figure 2: Example of an LSI SAS RAID Controller Configured with an LSISASx12
Expander
Flash ROM/ SAS
PCI Express
RAID Controller
SAS/SATA II Device
32-Bit Memory
Address/Data
Bus
PSBRAM/
I 2 C
SAS/SATA II Device
SAS/SATA II Device
SAS/SATA II Device
PCI Express Interface
NVSRAM
I 2 C
Interface
LSISASx12
Flash ROM/
NVSRAM/
SRAM
I 2 C/UART
LSISASx12
SAS/SATA II
Drives
PCI Express Interface
SAS/SATA
Drives
SAS/SATA II
Drives
SAS/SATA II
Drives
SAS/SATA II
Drives
8
SRAM
SRAM SDRAM
Peripheral
Bus
72-bit DDR/DDR2
with ECC
Interface
LSISAS1078
PCI Express to SAS ROC
SAS RAID Controller
Expander Expander