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AT91CAP9S250A

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Rainbow Electronics AT91CAP9S250A User Manual

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Rainbow Electronics AT91CAP9S250A User Manual | 1008 pages

Rainbow Electronics AT91CAP9S250A User Manual | 1008 pages

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Table of contents

Document Outline

Features
1. Description
2. AT91CAP9S500A/AT91CAP9S250A Block Diagram
3. Signal Description
4. Package and Pinout
- 4.1 400-ball BGA Package Outline
- 4.2 400-ball BGA Package Pinout
5. Power Considerations
- 5.1 Power Supplies
- 5.2 Power Consumption
- 5.3 Programmable I/O Lines Power Supplies
6. I/O Line Considerations
- 6.1 JTAG Port Pins
- 6.2 Test Pin
- 6.3 Reset Pins
- 6.4 PIO Controllers
- 6.5 Shutdown Logic Pins
7. Processor and Architecture
- 7.1 ARM926EJ-S Processor
- 7.2 Bus Matrix
- 7.3 Matrix Masters
- 7.4 Matrix Slaves
- 7.5 Master-to-Slave Access
- 7.6 Peripheral DMA Controller
- 7.7 DMA Controller
- 7.8 Debug and Test Features
8. Memories
- 8.1 Embedded Memories
  - 8.1.1 Internal Memory Mapping
  - 8.1.2 Boot Program
- 8.2 External Memories
9. System Controller
- 9.1 System Controller Block Diagram
- 9.2 Reset Controller
- 9.3 Shutdown Controller
- 9.4 Clock Generator
- 9.5 Power Management Controller
- 9.6 Periodic Interval Timer
- 9.7 Watchdog Timer
- 9.8 Real-time Timer
- 9.9 General-Purpose Backed-up Registers
- 9.10 Advanced Interrupt Controller
- 9.11 Debug Unit
- 9.12 Chip Identification
- 9.13 PIO Controllers
10. Peripherals
- 10.1 User Interface
- 10.2 Identifiers
  - 10.2.1 Peripheral Interrupts and Clock Control
- 10.3 Peripherals Signals Multiplexing on I/O Lines
- 10.4 Embedded Peripherals
11. Metal Programmable Block
- 11.1 Internal Connectivity
- 11.2 External Connectivity
  - 11.2.1 Dedicated I/O Lines
  - 11.2.2 UTMI+ Transceiver
- 11.3 Prototyping Solution
12. ARM926EJ-S Processor Overview
- 12.1 Overview
- 12.2 Block Diagram
- 12.3 ARM9EJ-S Processor
- 12.4 CP15 Coprocessor
  - 12.4.1 CP15 Registers Access
- 12.5 Memory Management Unit (MMU)
- 12.6 Caches and Write Buffer
  - 12.6.1 Instruction Cache (ICache)
  - 12.6.2 Data Cache (DCache) and Write Buffer
- 12.7 Tightly-Coupled Memory Interface
- 12.8 Bus Interface Unit
13. Debug and Test
- 13.1 Description
- 13.2 Block Diagram
- 13.3 Application Examples
  - 13.3.1 Debug Environment
  - 13.3.2 Test Environment
- 13.4 Debug and Test Pin Description
- 13.5 Functional Description
14. Boot Program
- 14.1 Description
- 14.2 Flow Diagram
- 14.3 Device Initialization
- 14.4 DataFlash Boot
- 14.5 NANDFlash Boot
  - 14.5.1 Supported NANDFlash Devices
- 14.6 SAM-BA Boot
- 14.7 Hardware and Software Constraints
15. Reset Controller (RSTC)
- 15.1 Description
- 15.2 Block Diagram
- 15.3 Functional Description
- 15.4 Reset Controller (RSTC) User Interface
16. Real-time Timer (RTT)
- 16.1 Overview
- 16.2 Block Diagram
- 16.3 Functional Description
- 16.4 Real-time Timer (RTT) User Interface
17. Periodic Interval Timer (PIT)
- 17.1 Overview
- 17.2 Block Diagram
- 17.3 Functional Description
- 17.4 Periodic Interval Timer (PIT) User Interface
18. Watchdog Timer (WDT)
- 18.1 Description
- 18.2 Block Diagram
- 18.3 Functional Description
- 18.4 Watchdog Timer (WDT) User Interface
19. Shutdown Controller (SHDWC)
- 19.1 Description
- 19.2 Block Diagram
- 19.3 I/O Lines Description
- 19.4 Product Dependencies
  - 19.4.1 Power Management
- 19.5 Functional Description
- 19.6 Shutdown Controller (SHDWC) User Interface
20. Bus Matrix
- 20.1 Description
- 20.2 Memory Mapping
- 20.3 Special Bus Granting Techniques
- 20.4 Arbitration
- 20.5 Bus Matrix User Interface
- 20.6 Chip Configuration User Interface
21. External Bus Interface (EBI)
- 21.1 Description
  - 21.1.1 External Bus Interface
- 21.2 I/O Lines Description
- 21.3 Application Example
  - 21.3.1 Hardware Interface
- 21.4 Product Dependencies
  - 21.4.1 I/O Lines
- 21.5 Functional Description
- 21.6 Implementation Examples
22. Static Memory Controller (SMC)
- 22.1 Description
- 22.2 I/O Lines Description
- 22.3 Multiplexed Signals
- 22.4 Application Example
  - 22.4.1 Hardware Interface
- 22.5 Product Dependencies
  - 22.5.1 I/O Lines
- 22.6 External Memory Mapping
- 22.7 Connection to External Devices
  - 22.7.1 Data Bus Width
  - 22.7.2 Byte Write or Byte Select Access
- 22.8 Standard Read and Write Protocols
- 22.9 Automatic Wait States
- 22.10 Data Float Wait States
- 22.11 External Wait
- 22.12 Slow Clock Mode
  - 22.12.1 Slow Clock Mode Waveforms
  - 22.12.2 Switching from (to) Slow Clock Mode to (from) Normal Mode
- 22.13 Asynchronous Page Mode
- 22.14 Static Memory Controller (SMC) User Interface
23. DDR/SDR SDRAM Controller (DDRSDRC)
- 23.1 Description
- 23.2 DDRSDRC Module Diagram
- 23.3 Product Dependencies
- 23.4 Functional Description
- 23.5 Software Interface / SDRAM Organization, Address Mapping
  - 23.5.1 SDRAM Address Mapping for 16-bit Memory Data Bus Width(1)
  - 23.5.2 SDR-SDRAM Address Mapping for 32-bit Memory Data Bus Width
- 23.6 DDR-SDRAMC User Interface
24. Burst Cellular RAM Controller (BCRAMC)
- 24.1 Description
- 24.2 BCRAMC Block Diagram
- 24.3 Product Dependencies
  - 24.3.1 Cellular Ram Initialization
- 24.4 Functional Description
- 24.5 BCRAMC User Interface
25. Error Corrected Code (ECC) Controller
- 25.1 Description
- 25.2 Block Diagram
- 25.3 Functional Description
  - 25.3.1 Write Access
  - 25.3.2 Read Access
- 25.4 Error Corrected Code (ECC) Controller User Interface
26. DMA Controller (DMAC)
- 26.1 Description
- 26.2 Block Diagram
- 26.3 Functional Description
- 26.4 DMA Controller Software Requirements
- 26.5 DMA Controller (DMAC) User Interface
27. Peripheral DMA Controller (PDC)
- 27.1 Description
- 27.2 Block Diagram
- 27.3 Functional Description
- 27.4 Peripheral DMA Controller (PDC) User Interface
28. Clock Generator
- 28.1 Description
- 28.2 Slow Clock Crystal Oscillator
- 28.3 Main Oscillator
- 28.4 Divider and PLL Block
29. Power Management Controller (PMC)
- 29.1 Description
- 29.2 Master Clock Controller
- 29.3 Processor Clock Controller
- 29.4 USB Clock Controller
- 29.5 Peripheral Clock Controller
- 29.6 Programmable Clock Output Controller
- 29.7 Programming Sequence
- 29.8 Clock Switching Details
  - 29.8.1 Master Clock Switching Timings
  - 29.8.2 Clock Switching Waveforms
- 29.9 Power Management Controller (PMC) User Interface
30. Advanced Interrupt Controller (AIC)
- 30.1 Description
- 30.2 Block Diagram
- 30.3 Application Block Diagram
- 30.4 AIC Detailed Block Diagram
- 30.5 I/O Line Description
- 30.6 Product Dependencies
- 30.7 Functional Description
- 30.8 Advanced Interrupt Controller (AIC) User Interface
31. Debug Unit (DBGU)
- 31.1 Description
- 31.2 Block Diagram
- 31.3 Product Dependencies
- 31.4 UART Operations
- 31.5 Debug Unit User Interface
32. Parallel Input/Output Controller (PIO)
- 32.1 Description
- 32.2 Block Diagram
- 32.3 Product Dependencies
- 32.4 Functional Description
- 32.5 I/O Lines Programming Example
- 32.6 User Interface
33. Serial Peripheral Interface (SPI)
- 33.1 Description
- 33.2 Block Diagram
- 33.3 Application Block Diagram
- 33.4 Signal Description
- 33.5 Product Dependencies
- 33.6 Functional Description
- 33.7 Serial Peripheral Interface (SPI) User Interface
34. Two-wire Interface (TWI)
- 34.1 Description
- 34.2 List of Abbreviations
- 34.3 Block Diagram
- 34.4 Application Block Diagram
  - 34.4.1 I/O Lines Description
- 34.5 Product Dependencies
- 34.6 Functional Description
  - 34.6.1 Transfer Format
  - 34.6.2 Modes of Operation
- 34.7 Master Mode
- 34.8 Multi-master Mode
  - 34.8.1 Definition
  - 34.8.2 Different Multi-master Modes
- 34.9 Slave Mode
- 34.10 Two-wire Interface (TWI) User Interface
35. Universal Synchronous/Asynchronous Receiver/Transceiver
- 35.1 Description
- 35.2 Block Diagram
- 35.3 Application Block Diagram
- 35.4 I/O Lines Description
- 35.5 Product Dependencies
- 35.6 Functional Description
- 35.7 USART User Interface
36. Serial Synchronous Controller (SSC)
- 36.1 Description
- 36.2 Block Diagram
- 36.3 Application Block Diagram
- 36.4 Pin Name List
- 36.5 Product Dependencies
- 36.6 Functional Description
- 36.7 SSC Application Examples
- 36.8 Synchronous Serial Controller (SSC) User Interface
37. AC’97 Controller (AC’97C)
- 37.1 Description
- 37.2 Block Diagram
- 37.3 Pin Name List
- 37.4 Application Block Diagram
- 37.5 Product Dependencies
- 37.6 Functional Description
- 37.7 AC’97 Controller (AC97C) User Interface
38. Timer Counter (TC)
- 38.1 Description
- 38.2 Block Diagram
- 38.3 Pin Name List
- 38.4 Product Dependencies
- 38.5 Functional Description
- 38.6 Timer Counter (TC) User Interface
39. Controller Area Network (CAN)
- 39.1 Description
- 39.2 Block Diagram
- 39.3 Application Block Diagram
- 39.4 I/O Lines Description
- 39.5 Product Dependencies
- 39.6 CAN Controller Features
- 39.7 Functional Description
- 39.8 Controller Area Network (CAN) User Interface
40. Pulse Width Modulation (PWM) Controller
- 40.1 Description
- 40.2 Block Diagram
- 40.3 I/O Lines Description
- 40.4 Product Dependencies
- 40.5 Functional Description
- 40.6 Pulse Width Modulation (PWM) Controller User Interface
41. MultiMedia Card Interface (MCI)
- 41.1 Description
- 41.2 Block Diagram
- 41.3 Application Block Diagram
- 41.4 Pin Name List
- 41.5 Product Dependencies
- 41.6 Bus Topology
- 41.7 MultiMedia Card Operations
  - 41.7.1 Command - Response Operation
- 41.8
- 41.9 SD/SDIO Card Operations
  - 41.9.1 SDIO Data Transfer Type
  - 41.9.2 SDIO Interrupts
- 41.10 MultiMedia Card Interface (MCI) User Interface
42. 10/100 Ethernet MAC (EMAC)
- 42.1 Description
- 42.2 Block Diagram
- 42.3 Functional Description
- 42.4 Programming Interface
  - 42.4.1 Initialization
- 42.5 10/100 Ethernet MAC (EMAC) User Interface
43. USB Host Port (UHP)
- 43.1 Description
- 43.2 Block Diagram
- 43.3 Product Dependencies
- 43.4 Functional Description
  - 43.4.1 Host Controller Interface
  - 43.4.2 Host Controller Driver
- 43.5 Typical Connection
44. USB High Speed Device Port (UDPHS)
- 44.1 Description
- 44.2 Block Diagram
- 44.3 Typical Connection
- 44.4 Functional Description
- 44.5 USB High Speed Device Port (UDPHS) User Interface
45. Image Sensor Interface (ISI)
- 45.1 Overview
- 45.2 Block Diagram
- 45.3 Functional Description
- 45.4 Image Sensor Interface (ISI) User Interface
46. Analog-to-Digital Converter (ADC)
- 46.1 Description
- 46.2 Block Diagram
- 46.3 Signal Description
- 46.4 Product Dependencies
- 46.5 Functional Description
- 46.6 Analog-to-digital Converter (ADC) User Interface
47. AT91CAP9 Electrical Characteristics
- 47.1 Absolute Maximum Ratings
- 47.2 DC Characteristics
- 47.3 Power Consumption
  - 47.3.1 Power Consumption versus Modes
- 47.4 32 kHz Crystal Oscillator Characteristics
- 47.5 12 MHz Main Oscillator Characteristics
- 47.6 PLLA and PLLB Characteristics
- 47.7 UTMI PLL Characteristics
- 47.8 USB HS Characteristics
- 47.9 ADC
- 47.10 Timings
48. AT91CAP9 Mechanical Characteristics
- 48.1 Thermal Considerations
  - 48.1.1 Thermal Data
  - 48.1.2 Junction Temperature
- 48.2 Package Drawing
- 48.3 Soldering Profile
49. AT91CAP9 Ordering Information
50. AT91CAP9 Errata
- 50.1 Marking
- 50.2 Errata
51. Revision History
Table of Contents

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