Rainbow Electronics AT91CAP9S250A - Manual (Page 394)

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6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
The Fast Forcing feature does not affect the Source 0 pending bit in the Interrupt Pending
Register (AIC_IPR).
The FIQ Vector Register (AIC_FVR) reads the contents of the Source Vector Register 0
(AIC_SVR0), whatever the source of the fast interrupt may be. The read of the FVR does not
clear the Source 0 when the fast forcing feature is used and the interrupt source should be
cleared by writing to the Interrupt Clear Command Register (AIC_ICCR).
All enabled and pending interrupt sources that have the fast forcing feature enabled and that
are programmed in edge-triggered mode must be cleared by writing to the Interrupt Clear
Command Register. In doing so, they are cleared independently and thus lost interrupts are
prevented.
The read of AIC_IVR does not clear the source that has the fast forcing feature enabled.
The source 0, reserved to the fast interrupt, continues operating normally and becomes one of
the Fast Interrupt sources.
Figure 30-10. Fast Forcing
30.7.5 Protect Mode
The Protect Mode permits reading the Interrupt Vector Register without performing the associ-
ated automatic operations. This is necessary when working with a debug system. When a
debugger, working either with a Debug Monitor or the ARM processor's ICE, stops the applica-
tions and updates the opened windows, it might read the AIC User Interface and thus the IVR.
This has undesirable consequences:
• If an enabled interrupt with a higher priority than the current one is pending, it is stacked.
• If there is no enabled pending interrupt, the spurious vector is returned.
In either case, an End of Interrupt command is necessary to acknowledge and to restore the
context of the AIC. This operation is generally not performed by the debug system as the
debug system would become strongly intrusive and cause the application to enter an undes-
ired state.
This is avoided by using the Protect Mode. Writing DBGM in AIC_DCR (Debug Control Regis-
ter) at 0x1 enables the Protect Mode.
When the Protect Mode is enabled, the AIC performs interrupt stacking only when a write
access is performed on the AIC_IVR. Therefore, the Interrupt Service Routines must write
Source 0
_
FIQ
Input Stage
Automatic Clear
Input Stage
Automatic Clear
Source n
AIC_IPR
AIC_IMR
AIC_FFSR
AIC_IPR
AIC_IMR
Priority
Manager
nFIQ
nIRQ
Read IVR if Source n is the current interrupt
and if Fast Forcing is disabled on Source n.
Read FVR if Fast Forcing is
disabled on Sources 1 to 31.