Rainbow Electronics AT91CAP9S250A - Manual (Page 281)

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6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
Figure 26-3. DMAC Transfer Hierarchy for Non-Memory Peripheral
Figure 26-4. DMAC Transfer Hierarchy for Memory
Buffer: A buffer of DMAC data. The amount of data (length) is determined by the flow controller.
For transfers between the DMAC and memory, a buffer is broken directly into a sequence of
AMBA bursts and AMBA single transfers. For transfers between the DMAC and a non-memory
peripheral, a buffer is broken into a sequence of DMAC transactions (single and chunks). These
are in turn broken into a sequence of AMBA transfers.
Transaction: A basic unit of a DMAC transfer as determined by either the hardware or software
handshaking interface. A transaction is only relevant for transfers between the DMAC and a
source or destination peripheral if the source or destination peripheral is a non-memory device.
There are two types of transactions: single transfer and chunk transfer.
– Single transfer: The length of a single transaction is always 1 and is converted to a
single AMBA access.
– Chunk transfer: The length of a chunk is programmed into the DMAC. The chunk is
then converted into a sequence of AHB access.DMAC executes each AMBA burst
transfer by performing incremental bursts that are no longer than 16 beats.
DMAC transfer: Software controls the number of buffers in a DMAC transfer. Once the DMAC
transfer has completed, then hardware within the DMAC disables the channel and can generate
HDMA Transfer DMA Transfer
Level
Buffer Buffer Buffer
Buffer Transfer
Level
Chunk
Transfer
Chunk
Transfer
Chunk
Transfer
Single
Transfer
DMA Transaction
Level
Burst
Transfer
AMBA
Burst
Transfer
AMBA
Burst
Transfer
AMBA
Single
Transfer
AMBA
AMBA Transfer
Level
Single
Transfer
AMBA
HDMA Transfer DMA Transfer
Level
Buffer Buffer Buffer
Buffer Transfer
Level
Burst
Transfer
AMBA
Burst
Transfer
AMBA
Burst
Transfer
AMBA
Single
Transfer
AMBA
AMBA Transfer
Level