Rainbow Electronics AT91CAP9S250A - Manual (Page 70)

70
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
13.4 Debug and Test Pin Description
13.5 Functional Description
13.5.1 Test Pin
One dedicated pin, TST, is used to define the device operating mode. The user must make
sure that this pin is tied at low level to ensure normal operating conditions. Other values asso-
ciated with this pin are reserved for manufacturing test.
13.5.2 Embedded In-circuit Emulator
The ARM9EJ-S Embedded In-Circuit Emulator-RT is supported via the ICE/JTAG port. It is
connected to a host computer via an ICE interface. Debug support is implemented using an
ARM9EJ-S core embedded within the ARM926EJ-S. The internal state of the ARM926EJ-S is
examined through an ICE/JTAG port which allows instructions to be serially inserted into the
pipeline of the core without using the external data bus. Therefore, when in debug state, a
store-multiple (STM) can be inserted into the instruction pipeline. This exports the contents of
the ARM9EJ-S registers. This data can be serially shifted out without affecting the rest of the
system.
There are two scan chains inside the ARM9EJ-S processor which support testing, debugging,
and programming of the EmbeddedICE-RT
™ . The scan chains are controlled by the ICE/JTAG
port.
EmbeddedICE mode is selected when JTAGSEL is low. It is not possible to switch directly
between ICE and JTAG operations. A chip reset must be performed after JTAGSEL is
changed.
For further details on the Embedded In-Circuit-Emulator-RT, see the ARM document:
Table 13-1. Debug and Test Pin List
Pin Name Function Type Active Level
Reset/Test
NRST Microcontroller Reset Input/Output Low
TST Test Mode Select Input High
ICE and JTAG
TCK Test Clock Input
TDI Test Data In Input
TDO Test Data Out Output
TMS Test Mode Select Input
RTCK Returned Test Clock Output
NTRST Test Reset Input Low
JTAGSEL JTAG Selection Input
Debug Unit
DRXD Debug Receive Data Input
DTXD Debug Transmit Data Output