Rainbow Electronics AT91CAP9S250A - Manual (Page 482)

482
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
• SCBR: Serial Clock Baud Rate
In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the Master Clock MCK. The
Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud
rate:
Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results.
At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer.
• DLYBS: Delay Before SPCK
This field defines the delay from NPCS valid to the first valid SPCK transition.
When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period.
Otherwise, the following equations determine the delay:
• DLYBCT: Delay Between Consecutive Transfers
This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.
The delay is always inserted after each transfer and before removing the chip select if needed.
When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the
character transfers.
Otherwise, the following equation determines the delay:
1100 Reserved
1101 Reserved
1110 Reserved
1111 Reserved
BITS Bits Per Transfer
SPCK Baudrate
MCK
SCBR
--------------- =
Delay Before SPCK
DLYBS
MCK
------------------- =
Delay Between Consecutive Transfers
32 DLYBCT
×
MCK
------------------------------------- =