Rainbow Electronics AT91CAP9S250A User Manual
Page 506
506
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
34.9.5.4
Clock Synchronization
In both read and write modes, it may happen that TWI_THR/TWI_RHR buffer is not filled /emp-
tied before the emission/reception of a new character. In this case, to avoid sending/receiving
undesired data, a clock stretching mechanism is implemented.
34.9.5.5
Clock Synchronization in Read Mode
The clock is tied low if the shift register is empty and if a STOP or REPEATED START condition
was not detected. It is tied low until the shift register is loaded.
describes the clock synchronization in Read mode.
Figure 34-27. Clock Synchronization in Read Mode
Notes:
1. TXRDY is reset when data has been written in the TWI_TH to the shift register and set when this data has been acknowl-
edged or non acknowledged.
2. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from
SADR.
3. SCLWS is automatically set when the clock synchronization mechanism is started.
DATA1
The clock is stretched after the ACK, the state of TWD is undefined during clock stretching
SCLWS
SVACC
SVREAD
TXRDY
TWCK
TWI_THR
TXCOMP
The data is memorized in TWI_THR until a new value is written
TWI_THR is transmitted to the shift register
Ack or Nack from the master
DATA0
DATA0
DATA2
1
2
1
CLOCK is tied low by the TWI
as long as THR is empty
S
SADR
S
R
DATA0
A
A
DATA1
A
DATA2
NA
S
XXXXXXX
2
Write THR
As soon as a START is detected