Rainbow Electronics AT91CAP9S250A Instruction Manuals and User Guides
We have 1 Instruction Manual and User Guide for AT91CAP9S250A Rainbow Electronics
Manuals 
| Recognized languages: | English |
|---|---|
| Pages: | 1008 |
| Size: | 10.56 MB |
Show table of contents
Document Outline
- Features
- 1. Description
- 2. AT91CAP9S500A/AT91CAP9S250A Block Diagram
- 3. Signal Description
- 4. Package and Pinout
- 5. Power Considerations
- 6. I/O Line Considerations
- 7. Processor and Architecture
- 8. Memories
- 9. System Controller
- 9.1 System Controller Block Diagram
- 9.2 Reset Controller
- 9.3 Shutdown Controller
- 9.4 Clock Generator
- 9.5 Power Management Controller
- 9.6 Periodic Interval Timer
- 9.7 Watchdog Timer
- 9.8 Real-time Timer
- 9.9 General-Purpose Backed-up Registers
- 9.10 Advanced Interrupt Controller
- 9.11 Debug Unit
- 9.12 Chip Identification
- 9.13 PIO Controllers
- 10. Peripherals
- 10.1 User Interface
- 10.2 Identifiers
- 10.3 Peripherals Signals Multiplexing on I/O Lines
- 10.4 Embedded Peripherals
- 10.4.1 Serial Peripheral Interface
- 10.4.2 Two-wire Interface
- 10.4.3 USART
- 10.4.4 Synchronous Serial Controller
- 10.4.5 AC97 Controller
- 10.4.6 Timer Counter
- 10.4.7 Pulse Width Modulation Controller
- 10.4.8 Multimedia Card Interface
- 10.4.9 CAN Controller
- 10.4.10 USB Host Port
- 10.4.11 USB High Speed Device Port
- 10.4.12 LCD Controller
- 10.4.13 Ethernet 10/100 MAC
- 10.4.14 Image Sensor Interface
- 11. Metal Programmable Block
- 12. ARM926EJ-S Processor Overview
- 13. Debug and Test
- 14. Boot Program
- 15. Reset Controller (RSTC)
- 16. Real-time Timer (RTT)
- 17. Periodic Interval Timer (PIT)
- 18. Watchdog Timer (WDT)
- 19. Shutdown Controller (SHDWC)
- 20. Bus Matrix
- 21. External Bus Interface (EBI)
- 22. Static Memory Controller (SMC)
- 22.1 Description
- 22.2 I/O Lines Description
- 22.3 Multiplexed Signals
- 22.4 Application Example
- 22.5 Product Dependencies
- 22.6 External Memory Mapping
- 22.7 Connection to External Devices
- 22.8 Standard Read and Write Protocols
- 22.9 Automatic Wait States
- 22.10 Data Float Wait States
- 22.11 External Wait
- 22.12 Slow Clock Mode
- 22.13 Asynchronous Page Mode
- 22.14 Static Memory Controller (SMC) User Interface
- 23. DDR/SDR SDRAM Controller (DDRSDRC)
- 24. Burst Cellular RAM Controller (BCRAMC)
- 25. Error Corrected Code (ECC) Controller
- 26. DMA Controller (DMAC)
- 26.1 Description
- 26.2 Block Diagram
- 26.3 Functional Description
- 26.4 DMA Controller Software Requirements
- 26.5 DMA Controller (DMAC) User Interface
- 26.5.1 DMAC Global Configuration Register
- 26.5.2 DMAC Enable Register
- 26.5.3 DMAC Software Single Request Register
- 26.5.4 DMAC Software Chunk Transfer Request Register
- 26.5.5 DMAC Software Last Transfer Flag Register
- 26.5.6 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Enable Register
- 26.5.7 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Disable Register
- 26.5.8 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Mask Register
- 26.5.9 DMAC Error, Buffer Transfer and Chained Buffer Transfer Status Register
- 26.5.10 DMAC Channel Handler Enable Register
- 26.5.11 DMAC Channel Handler Disable Register
- 26.5.12 DMAC Channel Handler Status Register
- 26.5.13 DMAC Channel x [x = 0..3] Source Address Register
- 26.5.14 DMAC Channel x [x = 0..3] Destination Address Register
- 26.5.15 DMAC Channel x [x = 0..3] Descriptor Address Register
- 26.5.16 DMAC Channel x [x = 0..3] Control A Register
- 26.5.17 DMAC Channel x [x = 0..3] Control B Register
- 26.5.18 DMAC Channel x [x = 0..3] Configuration Register
- 26.5.19 DMAC Channel x [x = 0..3] Source Picture in Picture Configuration Register
- 26.5.20 DMAC Channel x [x = 0..3] Destination Picture in Picture Configuration Register
- 27. Peripheral DMA Controller (PDC)
- 27.1 Description
- 27.2 Block Diagram
- 27.3 Functional Description
- 27.4 Peripheral DMA Controller (PDC) User Interface
- 27.4.1 Receive Pointer Register
- 27.4.2 Receive Counter Register
- 27.4.3 Transmit Pointer Register
- 27.4.4 Transmit Counter Register
- 27.4.5 Receive Next Pointer Register
- 27.4.6 Receive Next Counter Register
- 27.4.7 Transmit Next Pointer Register
- 27.4.8 Transmit Next Counter Register
- 27.4.9 Transfer Control Register
- 27.4.10 Transfer Status Register
- 28. Clock Generator
- 29. Power Management Controller (PMC)
- 29.1 Description
- 29.2 Master Clock Controller
- 29.3 Processor Clock Controller
- 29.4 USB Clock Controller
- 29.5 Peripheral Clock Controller
- 29.6 Programmable Clock Output Controller
- 29.7 Programming Sequence
- 29.8 Clock Switching Details
- 29.9 Power Management Controller (PMC) User Interface
- 29.9.1 PMC System Clock Enable Register
- 29.9.2 PMC System Clock Disable Register
- 29.9.3 PMC System Clock Status Register
- 29.9.4 PMC Peripheral Clock Enable Register
- 29.9.5 PMC Peripheral Clock Disable Register
- 29.9.6 PMC Peripheral Clock Status Register
- 29.9.7 PMC UTMI Clock Configuration Register
- 29.9.8 PMC Clock Generator Main Oscillator Register
- 29.9.9 PMC Clock Generator Main Clock Frequency Register
- 29.9.10 PMC Clock Generator PLL A Register
- 29.9.11 PMC Clock Generator PLL B Register
- 29.9.12 PMC Master Clock Register
- 29.9.13 PMC Programmable Clock Register
- 29.9.14 PMC Interrupt Enable Register
- 29.9.15 PMC Interrupt Disable Register
- 29.9.16 PMC Status Register
- 29.9.17 PMC Interrupt Mask Register
- 30. Advanced Interrupt Controller (AIC)
- 30.1 Description
- 30.2 Block Diagram
- 30.3 Application Block Diagram
- 30.4 AIC Detailed Block Diagram
- 30.5 I/O Line Description
- 30.6 Product Dependencies
- 30.7 Functional Description
- 30.8 Advanced Interrupt Controller (AIC) User Interface
- 30.8.1 Base Address
- 30.8.2 Register Mapping
- 30.8.3 AIC Source Mode Register
- 30.8.4 AIC Source Vector Register
- 30.8.5 AIC Interrupt Vector Register
- 30.8.6 AIC FIQ Vector Register
- 30.8.7 AIC Interrupt Status Register
- 30.8.8 AIC Interrupt Pending Register
- 30.8.9 AIC Interrupt Mask Register
- 30.8.10 AIC Core Interrupt Status Register
- 30.8.11 AIC Interrupt Enable Command Register
- 30.8.12 AIC Interrupt Disable Command Register
- 30.8.13 AIC Interrupt Clear Command Register
- 30.8.14 AIC Interrupt Set Command Register
- 30.8.15 AIC End of Interrupt Command Register
- 30.8.16 AIC Spurious Interrupt Vector Register
- 30.8.17 AIC Debug Control Register
- 30.8.18 AIC Fast Forcing Enable Register
- 30.8.19 AIC Fast Forcing Disable Register
- 30.8.20 AIC Fast Forcing Status Register
- 31. Debug Unit (DBGU)
- 31.1 Description
- 31.2 Block Diagram
- 31.3 Product Dependencies
- 31.4 UART Operations
- 31.5 Debug Unit User Interface
- 31.5.1 Debug Unit Control Register
- 31.5.2 Debug Unit Mode Register
- 31.5.3 Debug Unit Interrupt Enable Register
- 31.5.4 Debug Unit Interrupt Disable Register
- 31.5.5 Debug Unit Interrupt Mask Register
- 31.5.6 Debug Unit Status Register
- 31.5.7 Debug Unit Receiver Holding Register
- 31.5.8 Debug Unit Transmit Holding Register
- 31.5.9 Debug Unit Baud Rate Generator Register
- 31.5.10 Debug Unit Chip ID Register
- 31.5.11 Debug Unit Chip ID Extension Register
- 31.5.12 Debug Unit Force NTRST Register
- 32. Parallel Input/Output Controller (PIO)
- 32.1 Description
- 32.2 Block Diagram
- 32.3 Product Dependencies
- 32.4 Functional Description
- 32.4.1 Pull-up Resistor Control
- 32.4.2 I/O Line or Peripheral Function Selection
- 32.4.3 Peripheral A or B Selection
- 32.4.4 Output Control
- 32.4.5 Synchronous Data Output
- 32.4.6 Multi Drive Control (Open Drain)
- 32.4.7 Output Line Timings
- 32.4.8 Inputs
- 32.4.9 Input Glitch Filtering
- 32.4.10 Input Change Interrupt
- 32.5 I/O Lines Programming Example
- 32.6 User Interface
- 32.6.1 PIO Controller PIO Enable Register
- 32.6.2 PIO Controller PIO Disable Register
- 32.6.3 PIO Controller PIO Status Register
- 32.6.4 PIO Controller Output Enable Register
- 32.6.5 PIO Controller Output Disable Register
- 32.6.6 PIO Controller Output Status Register
- 32.6.7 PIO Controller Input Filter Enable Register
- 32.6.8 PIO Controller Input Filter Disable Register
- 32.6.9 PIO Controller Input Filter Status Register
- 32.6.10 PIO Controller Set Output Data Register
- 32.6.11 PIO Controller Clear Output Data Register
- 32.6.12 PIO Controller Output Data Status Register
- 32.6.13 PIO Controller Pin Data Status Register
- 32.6.14 PIO Controller Interrupt Enable Register
- 32.6.15 PIO Controller Interrupt Disable Register
- 32.6.16 PIO Controller Interrupt Mask Register
- 32.6.17 PIO Controller Interrupt Status Register
- 32.6.18 PIO Multi-driver Enable Register
- 32.6.19 PIO Multi-driver Disable Register
- 32.6.20 PIO Multi-driver Status Register
- 32.6.21 PIO Pull Up Disable Register
- 32.6.22 PIO Pull Up Enable Register
- 32.6.23 PIO Pull Up Status Register
- 32.6.24 PIO Peripheral A Select Register
- 32.6.25 PIO Peripheral B Select Register
- 32.6.26 PIO Peripheral A B Status Register
- 32.6.27 PIO Output Write Enable Register
- 32.6.28 PIO Output Write Disable Register
- 32.6.29 PIO Output Write Status Register
- 33. Serial Peripheral Interface (SPI)
- 34. Two-wire Interface (TWI)
- 34.1 Description
- 34.2 List of Abbreviations
- 34.3 Block Diagram
- 34.4 Application Block Diagram
- 34.5 Product Dependencies
- 34.6 Functional Description
- 34.7 Master Mode
- 34.8 Multi-master Mode
- 34.9 Slave Mode
- 34.10 Two-wire Interface (TWI) User Interface
- 34.10.1 TWI Control Register
- 34.10.2 TWI Master Mode Register
- 34.10.3 TWI Slave Mode Register
- 34.10.4 TWI Internal Address Register
- 34.10.5 TWI Clock Waveform Generator Register
- 34.10.6 TWI Status Register
- 34.10.7 TWI Interrupt Enable Register
- 34.10.8 TWI Interrupt Disable Register
- 34.10.9 TWI Interrupt Mask Register
- 34.10.10 TWI Receive Holding Register
- 34.10.11 TWI Transmit Holding Register
- 35. Universal Synchronous/Asynchronous Receiver/Transceiver
- 35.1 Description
- 35.2 Block Diagram
- 35.3 Application Block Diagram
- 35.4 I/O Lines Description
- 35.5 Product Dependencies
- 35.6 Functional Description
- 35.7 USART User Interface
- 35.7.1 USART Control Register
- 35.7.2 USART Mode Register
- 35.7.3 USART Interrupt Enable Register
- 35.7.4 USART Interrupt Disable Register
- 35.7.5 USART Interrupt Mask Register
- 35.7.6 USART Channel Status Register
- 35.7.7 USART Receive Holding Register
- 35.7.8 USART Transmit Holding Register
- 35.7.9 USART Baud Rate Generator Register
- 35.7.10 USART Receiver Time-out Register
- 35.7.11 USART Transmitter Timeguard Register
- 35.7.12 USART FI DI RATIO Register
- 35.7.13 USART Number of Errors Register
- 35.7.14 USART Manchester Configuration Register
- 35.7.15 USART IrDA FILTER Register
- 36. Serial Synchronous Controller (SSC)
- 36.1 Description
- 36.2 Block Diagram
- 36.3 Application Block Diagram
- 36.4 Pin Name List
- 36.5 Product Dependencies
- 36.6 Functional Description
- 36.7 SSC Application Examples
- 36.8 Synchronous Serial Controller (SSC) User Interface
- 36.8.1 SSC Control Register
- 36.8.2 SSC Clock Mode Register
- 36.8.3 SSC Receive Clock Mode Register
- 36.8.4 SSC Receive Frame Mode Register
- 36.8.5 SSC Transmit Clock Mode Register
- 36.8.6 SSC Transmit Frame Mode Register
- 36.8.7 SSC Receive Holding Register
- 36.8.8 SSC Transmit Holding Register
- 36.8.9 SSC Receive Synchronization Holding Register
- 36.8.10 SSC Transmit Synchronization Holding Register
- 36.8.11 SSC Receive Compare 0 Register
- 36.8.12 SSC Receive Compare 1 Register
- 36.8.13 SSC Status Register
- 36.8.14 SSC Interrupt Enable Register
- 36.8.15 SSC Interrupt Disable Register
- 36.8.16 SSC Interrupt Mask Register
- 37. AC’97 Controller (AC’97C)
- 37.1 Description
- 37.2 Block Diagram
- 37.3 Pin Name List
- 37.4 Application Block Diagram
- 37.5 Product Dependencies
- 37.6 Functional Description
- 37.7 AC’97 Controller (AC97C) User Interface
- 37.7.1 AC’97 Controller Mode Register
- 37.7.2 AC’97 Controller Input Channel Assignment Register
- 37.7.3 AC’97 Controller Output Channel Assignment Register
- 37.7.4 AC’97 Controller Codec Channel Receive Holding Register
- 37.7.5 AC’97 Controller Codec Channel Transmit Holding Register
- 37.7.6 AC’97 Controller Channel A, Channel B, Channel C Receive Holding Register
- 37.7.7 AC’97 Controller Channel A, Channel B, Channel C Transmit Holding Register
- 37.7.8 AC’97 Controller Channel A Status Register
- 37.7.9 AC’97 Controller Channel B Status Register
- 37.7.10 AC’97 Controller Channel C Status Register
- 37.7.11 AC’97 Controller Codec Channel Status Register
- 37.7.12 AC’97 Controller Channel A Mode Register
- 37.7.13 AC’97 Controller Channel B Mode Register
- 37.7.14 AC’97 Controller Channel C Mode Register
- 37.7.15 AC’97 Controller Codec Channel Mode Register
- 37.7.16 AC’97 Controller Status Register
- 37.7.17 AC’97 Controller Interrupt Enable Register
- 37.7.18 AC’97 Controller Interrupt Disable Register
- 37.7.19 AC’97 Controller Interrupt Mask Register
- 38. Timer Counter (TC)
- 38.1 Description
- 38.2 Block Diagram
- 38.3 Pin Name List
- 38.4 Product Dependencies
- 38.5 Functional Description
- 38.5.1 TC Description
- 38.5.2 16-bit Counter
- 38.5.3 Clock Selection
- 38.5.4 Clock Control
- 38.5.5 TC Operating Modes
- 38.5.6 Trigger
- 38.5.7 Capture Operating Mode
- 38.5.8 Capture Registers A and B
- 38.5.9 Trigger Conditions
- 38.5.10 Waveform Operating Mode
- 38.5.11 Waveform Selection
- 38.5.12 External Event/Trigger Conditions
- 38.5.13 Output Controller
- 38.6 Timer Counter (TC) User Interface
- 38.6.1 TC Block Control Register
- 38.6.2 TC Block Mode Register
- 38.6.3 TC Channel Control Register
- 38.6.4 TC Channel Mode Register: Capture Mode
- 38.6.5 TC Channel Mode Register: Waveform Mode
- 38.6.6 TC Counter Value Register
- 38.6.7 TC Register A
- 38.6.8 TC Register B
- 38.6.9 TC Register C
- 38.6.10 TC Status Register
- 38.6.11 TC Interrupt Enable Register
- 38.6.12 TC Interrupt Disable Register
- 38.6.13 TC Interrupt Mask Register
- 39. Controller Area Network (CAN)
- 39.1 Description
- 39.2 Block Diagram
- 39.3 Application Block Diagram
- 39.4 I/O Lines Description
- 39.5 Product Dependencies
- 39.6 CAN Controller Features
- 39.7 Functional Description
- 39.8 Controller Area Network (CAN) User Interface
- 39.8.1 CAN Mode Register
- 39.8.2 CAN Interrupt Enable Register
- 39.8.3 CAN Interrupt Disable Register
- 39.8.4 CAN Interrupt Mask Register
- 39.8.5 CAN Status Register
- 39.8.6 CAN Baudrate Register
- 39.8.7 CAN Timer Register
- 39.8.8 CAN Timestamp Register
- 39.8.9 CAN Error Counter Register
- 39.8.10 CAN Transfer Command Register
- 39.8.11 CAN Abort Command Register
- 39.8.12 CAN Message Mode Register
- 39.8.13 CAN Message Acceptance Mask Register
- 39.8.14 CAN Message ID Register
- 39.8.15 CAN Message Family ID Register
- 39.8.16 CAN Message Status Register
- 39.8.17 CAN Message Data Low Register
- 39.8.18 CAN Message Data High Register
- 39.8.19 CAN Message Control Register
- 40. Pulse Width Modulation (PWM) Controller
- 40.1 Description
- 40.2 Block Diagram
- 40.3 I/O Lines Description
- 40.4 Product Dependencies
- 40.5 Functional Description
- 40.6 Pulse Width Modulation (PWM) Controller User Interface
- 40.6.1 PWM Mode Register
- 40.6.2 PWM Enable Register
- 40.6.3 PWM Disable Register
- 40.6.4 PWM Status Register
- 40.6.5 PWM Interrupt Enable Register
- 40.6.6 PWM Interrupt Disable Register
- 40.6.7 PWM Interrupt Mask Register
- 40.6.8 PWM Interrupt Status Register
- 40.6.9 PWM Channel Mode Register
- 40.6.10 PWM Channel Duty Cycle Register
- 40.6.11 PWM Channel Period Register
- 40.6.12 PWM Channel Counter Register
- 40.6.13 PWM Channel Update Register
- 41. MultiMedia Card Interface (MCI)
- 41.1 Description
- 41.2 Block Diagram
- 41.3 Application Block Diagram
- 41.4 Pin Name List
- 41.5 Product Dependencies
- 41.6 Bus Topology
- 41.7 MultiMedia Card Operations
- 41.8
- 41.9 SD/SDIO Card Operations
- 41.10 MultiMedia Card Interface (MCI) User Interface
- 41.10.1 MCI Control Register
- 41.10.2 MCI Mode Register
- 41.10.3 MCI Data Timeout Register
- 41.10.4 MCI SDCard/SDIO Register
- 41.10.5 MCI Argument Register
- 41.10.6 MCI Command Register
- 41.10.7 MCI Block Register
- 41.10.8 MCI Response Register
- 41.10.9 MCI Receive Data Register
- 41.10.10 MCI Transmit Data Register
- 41.10.11 MCI Status Register
- 41.10.12 MCI Interrupt Enable Register
- 41.10.13 MCI Interrupt Disable Register
- 41.10.14 MCI Interrupt Mask Register
- 42. 10/100 Ethernet MAC (EMAC)
- 42.1 Description
- 42.2 Block Diagram
- 42.3 Functional Description
- 42.3.1 Memory Interface
- 42.3.2 Transmit Block
- 42.3.3 Pause Frame Support
- 42.3.4 Receive Block
- 42.3.5 Address Checking Block
- 42.3.6 Broadcast Address
- 42.3.7 Hash Addressing
- 42.3.8 Copy All Frames (or Promiscuous Mode)
- 42.3.9 Type ID Checking
- 42.3.10 VLAN Support
- 42.3.11 PHY Maintenance
- 42.3.12 Media Independent Interface
- 42.4 Programming Interface
- 42.5 10/100 Ethernet MAC (EMAC) User Interface
- 42.5.1 Network Control Register
- 42.5.2 Network Configuration Register
- 42.5.3 Network Status Register
- 42.5.4 Transmit Status Register
- 42.5.5 Receive Buffer Queue Pointer Register
- 42.5.6 Transmit Buffer Queue Pointer Register
- 42.5.7 Receive Status Register
- 42.5.8 Interrupt Status Register
- 42.5.9 Interrupt Enable Register
- 42.5.10 Interrupt Disable Register
- 42.5.11 Interrupt Mask Register
- 42.5.12 PHY Maintenance Register
- 42.5.13 Pause Time Register
- 42.5.14 Hash Register Bottom
- 42.5.15 Hash Register Top
- 42.5.16 Specific Address 1 Bottom Register
- 42.5.17 Specific Address 1 Top Register
- 42.5.18 Specific Address 2 Bottom Register
- 42.5.19 Specific Address 2 Top Register
- 42.5.20 Specific Address 3 Bottom Register
- 42.5.21 Specific Address 3 Top Register
- 42.5.22 Specific Address 4 Bottom Register
- 42.5.23 Specific Address 4 Top Register
- 42.5.24 Type ID Checking Register
- 42.5.25 User Input/Output Register
- 42.5.26 EMAC Statistic Registers
- 43. USB Host Port (UHP)
- 44. USB High Speed Device Port (UDPHS)
- 44.1 Description
- 44.2 Block Diagram
- 44.3 Typical Connection
- 44.4 Functional Description
- 44.4.1 USB V2.0 High Speed Device Port Introduction
- 44.4.2 USB V2.0 High Speed Transfer Types
- 44.4.3 USB Transfer Event Definitions
- 44.4.4 USB V2.0 High Speed BUS Transactions
- 44.4.5 Endpoint Configuration
- 44.4.6 Transfer With DMA
- 44.4.7 Transfer Without DMA
- 44.4.8 Handling Transactions with USB V2.0 Device Peripheral
- 44.4.9 Speed Identification
- 44.4.10 USB V2.0 High Speed Global Interrupt
- 44.4.11 Endpoint Interrupts
- 44.4.12 Power Modes
- 44.4.13 Test Mode
- 44.5 USB High Speed Device Port (UDPHS) User Interface
- 44.5.1 UDPHS Control Register
- 44.5.2 UDPHS Frame Number Register
- 44.5.3 UDPHS Interrupt Enable Register
- 44.5.4 UDPHS Interrupt Status Register
- 44.5.5 UDPHS Clear Interrupt Register
- 44.5.6 UDPHS Endpoints Reset Register
- 44.5.7 UDPHS Test Register
- 44.5.8 UDPHS Endpoint Configuration Register
- 44.5.9 UDPHS Endpoint Control Enable Register
- 44.5.10 UDPHS Endpoint Control Disable Register
- 44.5.11 UDPHS Endpoint Control Register
- 44.5.12 UDPHS Endpoint Set Status Register
- 44.5.13 UDPHS Endpoint Clear Status Register
- 44.5.14 UDPHS Endpoint Status Register
- 44.5.15 UDPHS DMA Channel Transfer Descriptor
- 44.5.16 UDPHS DMA Next Descriptor Address Register
- 44.5.17 UDPHS DMA Channel Address Register
- 44.5.18 UDPHS DMA Channel Control Register
- 44.5.19 UDPHS DMA Channel Status Register
- 45. Image Sensor Interface (ISI)
- 45.1 Overview
- 45.2 Block Diagram
- 45.3 Functional Description
- 45.4 Image Sensor Interface (ISI) User Interface
- 45.4.1 ISI Control 1 Register
- 45.4.2 ISI Control 2 Register
- 45.4.3 ISI Status Register
- 45.4.4 Interrupt Enable Register
- 45.4.5 ISI Interrupt Disable Register
- 45.4.6 ISI Interrupt Mask Register
- 45.4.7 ISI Preview Register
- 45.4.8 ISI Preview Decimation Factor Register
- 45.4.9 ISI Preview Primary FBD Register
- 45.4.10 ISI Codec DMA Base Address Register
- 45.4.11 ISI Color Space Conversion YCrCb to RGB Set 0 Register
- 45.4.12 ISI Color Space Conversion YCrCb to RGB Set 1 Register
- 45.4.13 ISI Color Space Conversion RGB to YCrCb Set 0 Register
- 45.4.14 ISI Color Space Conversion RGB to YCrCb Set 1 Register
- 45.4.15 ISI Color Space Conversion RGB to YCrCb Set 2 Register
- 46. Analog-to-Digital Converter (ADC)
- 46.1 Description
- 46.2 Block Diagram
- 46.3 Signal Description
- 46.4 Product Dependencies
- 46.5 Functional Description
- 46.6 Analog-to-digital Converter (ADC) User Interface
- 46.6.1 ADC Control Register
- 46.6.2 ADC Mode Register
- 46.6.3 ADC Channel Enable Register
- 46.6.4 ADC Channel Disable Register
- 46.6.5 ADC Channel Status Register
- 46.6.6 ADC Status Register
- 46.6.7 ADC Last Converted Data Register
- 46.6.8 ADC Interrupt Enable Register
- 46.6.9 ADC Interrupt Disable Register
- 46.6.10 ADC Interrupt Mask Register
- 46.6.11 ADC Channel Data Register
- 47. AT91CAP9 Electrical Characteristics
- 48. AT91CAP9 Mechanical Characteristics
- 49. AT91CAP9 Ordering Information
- 50. AT91CAP9 Errata
- 51. Revision History
- Table of Contents