Rainbow Electronics AT91CAP9S250A - Manual (Page 388)

388
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
30.7.2 Interrupt Latencies
Global interrupt latencies depend on several parameters, including:
• The time the software masks the interrupts.
• Occurrence, either at the processor level or at the AIC level.
• The execution time of the instruction in progress when the interrupt occurs.
• The treatment of higher priority interrupts and the resynchronization of the hardware
signals.
This section addresses only the hardware resynchronizations. It gives details of the latency
times between the event on an external interrupt leading in a valid interrupt (edge or level) or
the assertion of an internal interrupt source and the assertion of the nIRQ or nFIQ line on the
processor. The resynchronization time depends on the programming of the interrupt source
and on its type (internal or external). For the standard interrupt, resynchronization times are
given assuming there is no higher priority in progress.
The PIO Controller multiplexing has no effect on the interrupt latencies of the external interrupt
sources.
30.7.2.1 External Interrupt Edge Triggered Source
Figure 30-6. External Interrupt Edge Triggered Source
30.7.2.2 External Interrupt Level Sensitive Source
Figure 30-7. External Interrupt Level Sensitive Source
Maximum FIQ Latency = 4 Cycles
Maximum IRQ Latency = 4 Cycles
nFIQ
nIRQ
MCK
IRQ or FIQ
(Positive Edge)
IRQ or FIQ
(Negative Edge)
Maximum IRQ
Latency = 3 Cycles
Maximum FIQ
Latency = 3 cycles
MCK
IRQ or FIQ
(High Level)
IRQ or FIQ
(Low Level)
nIRQ
nFIQ