Rainbow Electronics AT91CAP9S250A User Manual
Page 230
230
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
23.5
Software Interface / SDRAM Organization, Address Mapping
The SDRAM address space is organized into banks, rows and columns. The DDRSDRC maps
different memory types depending on the values set in the
DDRSDRC Configuration Register.
Section 23.6.3 ”DDRSDRC Configuration Register” on page 235
. The following figures illus-
trate the relation between CPU addresses and columns, rows and banks addresses for 16-bit
memory data bus widths and 32-bit memory data bus widths.
The DDRSDRC supports address mapping in linear mode.
Linear mode is a method for address mapping where banks alternate at each last SDRAM page
of current bank.
The DDRSDRC makes the SDRAM devices access protocol transparent to the user.
to
illustrate the SDRAM device memory mapping seen by the user in correlation with
the device structure. Various configurations are illustrated.
23.5.1
SDRAM Address Mapping for 16-bit Memory Data Bus Width
Table 23-1.
Linear Mapping for SDRAM Configuration, 2K Rows, 512/1024/2048/4096 Columns
CPU Address Line
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bk[1:0]
Row[10:0]
Column[8:0]
M0
Bk[1:0]
Row[10:0]
Column[9:0]
M0
Bk[1:0]
Row[10:0]
Column[10:0]
M0
Bk[1:0]
Row[10:0]
Column[11:0]
M0
Table 23-2.
Linear Mapping for SDRAM Configuration: 4K Rows, 512/1024/2048/4096 Columns
CPU Address Line
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bk[1:0]
Row[11:0]
Column[8:0]
M0
Bk[1:0]
Row[11:0]
Column[9:0]
M0
Bk[1:0]
Row[11:0]
Column[10:0]
M0
Bk[1:0]
Row[11:0]
Column[11:0]
M0
Table 23-3.
Linear Mapping for SDRAM Configuration: 8K Rows, 512/1024/2048/4096 Columns
CPU Address Line
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bk[1:0]
Row[12:0]
Column[8:0]
M0
Bk[1:0]
Row[12:0]
Column[9:0]
M0
Bk[1:0]
Row[12:0]
Column[10:0]
M0
Bk[1:0]
Row[12:0]
Column[11:0]
M0