Rainbow Electronics AT91CAP9S250A User Manual
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302
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
automatic transfer mode bit should remain enabled to keep the DMAC in Row 11 as
shown in
b.
If the buffer complete interrupt is masked (DMAC_EBCIMR.BTC[x] = ‘1’, where x is
the channel number) then hardware does not stall until it detects a write to the
buffer transfer completed interrupt enable register but starts the next buffer transfer
immediately. In this case software must clear the automatic mode bit,
DMAC_CTRLBx.AUTO, to put the device into ROW 1 of
before the last buffer of the DMAC transfer has completed.
The transfer is similar to that shown in
.
The DMAC Transfer flow is shown in
Figure 26-14. Multi-buffer Transfer with Source Address Auto-reloaded and Contiguous Destination Address
Address of
Source Layer
Address of
Destination Layer
Source Buffers
Destination Buffers
SADDR
Buffer0
Buffer1
Buffer2
DADDR(1)
DADDR(0)
DADDR(2)