Rainbow Electronics AT91CAP9S250A - Manual (Page 507)

507
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
34.9.5.6 Clock Synchronization in Write Mode
T h e c lo c k i s t i e d lo w i f t h e s h i f t r e g i s t e r a n d t h e T W I _ R H R i s f u l l . I f a S T O P o r
REPEATED_START condition was not detected, it is tied low until TWI_RHR is read.
Figure 34-28 on page 507 describes the clock synchronization in Read mode.
Figure 34-28. Clock Synchronization in Write Mode
Notes: 1. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from
SADR.
2. SCLWS is automatically set when the clock synchronization mechanism is started and automatically reset when the mecha-
nism is finished.
Rd DATA0
Rd DATA1
Rd DATA2
SVACC
SVREAD
RXRDY
SCLWS
TXCOMP
DATA1 DATA2
SCL is stretched on the last bit of DATA1
As soon as a START is detected
TWCK
TWD
TWI_RHR
CLOCK is tied low by the TWI as long as RHR is full
DATA0 is not read in the RHR
ADR S SADR W A DATA0 A A DATA2 DATA1 S NA