2 ddr-sdram initialization – Rainbow Electronics AT91CAP9S250A User Manual
Page 214
214
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
timer count register must to be set with (15.625 /100 MHz) = 1562 i.e. 0x061A or (7.81
/100 MHz) = 781 i.e. 0x030d
After initialization, the SDR-SDRAM device is fully functional.
23.3.2
DDR-SDRAM Initialization
The initialization sequence is generated by software. The DDR-SDRAM devices are initialized
by the following sequence:
1.
Program the memory device type into the configuration register (see
2.
Program the features of DDR-SDRAM device into the Timing Register (asynchronous
timing (trc, tras, etc.)), and into the Configuration Register (number of columns, rows,
banks, cas latency and output drive strength) (see
and
).
3.
An NOP command is issued to the DDR-SDRAM. Program the NOP command into the
Mode Register, the application must set Mode to 1 in the Mode Register (see
). Perform a write access to any DDR-SDRAM address to acknowl-
edge this command. Now clocks which drive DDR-SDRAM device are enabled.
A minimum pause of 200 µs is provided to precede any signal toggle.
4.
An NOP command is issued to the DDR-SDRAM. Program the NOP command into the
Mode Register, the application must set Mode to 1 in the Mode Register (see
). Perform a write access to any DDR-SDRAM address to acknowl-
edge this command. Now CKE is driven high.
5.
An all banks precharge command is issued to the DDR-SDRAM. Program all banks
precharge command into the Mode Register, the application must set Mode to 2 in the
Mode Register (See
). Perform a write access to any DDR-
SDRAM address to acknowledge this command.
6.
An Extended Mode Register set (EMRS) cycle is issued to enable DLL and to program
output drive strength (DIC/DS). The application must set Mode to 5 in the Mode Regis-
ter (see
) and perform a write access to the DDR-SDRAM
to acknowledge this command. The write address must be chosen so that BA[1] or
BA[0] are set to 1. For example, with a 16-bit 128 MB DDR-SDRAM (12 rows, 9 col-
umns, 4 banks) bank address, the DDR-SDRAM write access should be done at the
address 0x20800000 or 0x20400000.
An additional 200 cycles of clock are required for locking DLL
7.
Program DLL field into the Configuration Register (see
) to
high (Enable DLL reset).
8.
A Mode Register set (MRS) cycle is issued to reset DLL. The application must set
Mode to 3 in the Mode Register (see
) and perform a write
access to the DDR-SDRAM to acknowledge this command. The write address must be
chosen so that BA[1:0] bits are set to 0. For example, with a 16-bit 128 MB DDR-
SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should
be done at the address 0x20000000.
9.
Two auto-refresh (CBR) cycles are provided. Program the auto refresh command
(CBR) into the Mode Register, the application must set Mode to 4 in the Mode Register
(see
). Performs a write access to any DDR-SDRAM loca-
tion twice to acknowledge these commands.
10. Program DLL field into the Configuration Register (see
) to
low (Disable DLL reset).