Rainbow Electronics AT91CAP9S250A - Manual (Page 976)

976
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
47.10.6 DDR SDRAMC Timings
The DDR SDRAM controller satisfies the timings of standard Mobile SDRAM, timings for which
are given in
Table 47-35 , in MAX and STH corners.
Timings are given assuming a capacitance load on data, control and address pads :
Notes: 1. Control/Address is the set of following timings : A0-A9, A11-A13, SDA10, SDCKE, SDCS, RAS, CAS, BAx and SDWE.
2. Data out refer to D0-D7 sampled by DQS0 or to D8-D15 sampled by DQS1.
3. DQM refer to DQM0 sampled by DQS0 or to DQM1 sampled by DQS1.
4. Data in refer to D0-D7 sampled by DQS0 or to D8-D15 sampled by DQS1.
Table 47-32. Capacitance Load on Data, Control and Address Pads
Corner
MAX STH MIN
20 pF 20 pF 0 pF
Table 47-33. Capacitance Load on SDCK Pad
Corner
MAX STH MIN
10pF 10 pF 10 pF
Table 47-34. DDRSDRC Timings
Symbol Parameter Min Max Units
DDR
1
Control/Address out valid before SDCK Rising Edge (1) 0.5* t
CPMCK+
TBD ns
DDR
2
Control/Address out change after SDCK Rising Edge (1) 0.5* t
CPMCK+
TBD ns
DDR
3
DQS out delay to SDCK Edges TBD TBD ns
DDR
4
Data out (2) and DQM (3) valid before DQS out Edges TBD ns
DDR
5
Data out (2) and DQM (3) change after DQS out Edges TBD ns
DDR
6
Data in (4) Skew from DQS in Edges TBD ns
DDR
7
Data in (4) Hold after DQS in Edges TBD ns