Rainbow Electronics AT91CAP9S250A - Manual (Page 904)

904
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
44.5.15 UDPHS DMA Channel Transfer Descriptor
The DMA channel transfer descriptor is loaded from the memory.
Be careful with the alignment of this buffer.
The structure of the DMA channel transfer descriptor is defined by three parameters as
described below:
Offset 0:
The address must be aligned: 0xXXXX0
Next Descriptor Address Register: UDPHS_DMANXTDSCx
Offset 4:
The address must be aligned: 0xXXXX4
DMA Channelx Address Register: UDPHS_DMAADDRESSx
Offset 8:
The address must be aligned: 0xXXXX8
DMA Channelx Control Register: UDPHS_DMACONTROLx
To use the DMA channel transfer descriptor, fill the structures with the correct value (as
described in the following pages).
Then write directly in UDPHS_DMANXTDSCx the address of the descriptor to be used first.
Then write 1 in the LDNXT_DSC bit of UDPHS_DMACONTROLx (load next channel transfer
descriptor). The descriptor is automatically loaded upon Endpointx request for packet transfer.