Rainbow Electronics AT91CAP9S250A - Manual (Page 473)

473
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
If PCSDEC = 1:
NPCS[3:0] output signals = PCS.
• DLYBCS: Delay Between Chip Selects
This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees non-over-
lapping chip selects and solves bus contentions in case of peripherals having long data float times.
If DLYBCS is less than or equal to six, six MCK periods are inserted by default.
Otherwise, the following equation determines the delay:
Delay Between Chip Selects
DLYBCS
MCK
----------------------- =