Rainbow Electronics AT91CAP9S250A - Manual (Page 251)

251
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
Figure 24-6. Four Beat Wrapping Burst With Address Starting at 0x0C
Figure 24-7. Write Command Followed by a Read Command then Interrupt Write Burst
24.4.3 BCRAMC Read Cycle
The BCRAMC allows burst access or single access.
The Cellular Ram device is programmed with a continuous burst length.
The latency from read command to data output is dependant on the Cellular Ram version. The
owait signal is monitored to detect any conflict of refresh collision.
To initiate a single access, the BCRAMC generates an initial burst read command. To comply
with Cellular Ram timing parameters, additional clock cycles are inserted to check programmed
D0 D2 D3 D1
Latency = 3 Latency = 5
Refresh Collision No Refresh Collision
A[27:0]
BCADV
BCCS
BCCK
BCCRE
D[31:0]
BCOE
BCWE
BCOWAIT
Latency = 3
Refresh collision No Refresh collision
D0 D1 D2 D3 D0 D1 D2 D3
Latency = 5
A[27:0]
BCADV
BCCS
BCCK
BCCRE
D[31:0]
BCOE
BCWE
BCOWAIT