11 pwm channel period register – Rainbow Electronics AT91CAP9S250A User Manual
Page 756
756
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
40.6.11
PWM Channel Period Register
Register Name:
PWM_CPRDx
Access Type:
Read/Write
Only the first 16 bits (internal channel counter size) are significant.
• CPRD: Channel Period
If the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be
calculated:
– By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128,
256, 512, or 1024). The resulting period formula will be:
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
or
If the waveform is center-aligned, then the output waveform period depends on the counter source clock and can be
calculated:
– By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128,
256, 512, or 1024). The resulting period formula will be:
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
or
31
30
29
28
27
26
25
24
CPRD
23
22
21
20
19
18
17
16
CPRD
15
14
13
12
11
10
9
8
CPRD
7
6
5
4
3
2
1
0
CPRD
X
CPRD
×
(
)
MCK
--------------------------------
CRPD
DIVA
×
(
)
MCK
-------------------------------------------
CRPD
DIVAB
×
(
)
MCK
-----------------------------------------------
2
X
CPRD
Ч
Ч
(
)
MCK
-------------------------------------------
2
CPRD
DIVA
Ч
Ч
(
)
MCK
------------------------------------------------------
2
CPRD
×
DIVB
×
(
)
MCK
------------------------------------------------------