6 ddrsdrc low-power register – Rainbow Electronics AT91CAP9S250A User Manual
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6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
23.6.6
DDRSDRC Low-power Register
Register Name:
DDRSDRC_LPR
Access Type:
Read/Write
Reset Value:
See
• LPCB: Low-power Command Bit
Reset value is “00”.
00: Low-power Feature is inhibited: no power-down, self refresh and Deep power mode are issued to the SDRAM device.
01: The DDRSDRAMC issues a Self Refresh Command to the SDRAM device, the clock(s) is/are de-activated and the
CKE signal is set low. The SDRAM device leaves the self refresh mode when accessed and enters it after the access.
10: The DDRSDRC issues a Power-down Command to the SDRAM device after each access, the CKE signal is set low.
The SDRAM device leaves the power-down mode when accessed and enters it after the access.
11: The DDRSDRC issues a Deep Power-down Command to the Mobile SDRAM device.This mode is unique to Mobile
SDRAM devices.
• CLK_FR: Clock frozen Command Bit
Reset value is “0”.
This field sets the clock low during power-down mode. Some SDRAM devices do not support freezing the clock during
power-down mode. Refer to the device datasheet for details on this.
1: Clock(s) is/are frozen.
0: Clock(s) is/are not frozen.
• PASR: Partial Array Self Refresh
Reset value is “0”.
This field is unique to Mobile SDRAM. It is used to specify whether only one quarter, one half or all banks of the SDRAM
array are enabled. Disabled banks are not refreshed in self refresh mode.
The values of this field are dependant on Mobile SDRAM devices.
After the initialization sequence, as soon as PASR field is modified and self refresh mode is activated, Extended Mode Reg-
ister is accessed automatically and PASR bits are updated before entering self refresh mode.
• TCR: Temperature compensated self refresh
Reset value is “0”.
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
TIMEOUT
DS
TCR
7
6
5
4
3
2
1
0
–
PASR
CLK_FR
LPCB