Rainbow Electronics AT91CAP9S250A - Manual (Page 306)

306
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
Figure 26-17. DMAC Transfer Flow for Linked List Source Address and Contiguous Destination Address
26.3.6 Disabling a Channel Prior to Transfer Completion
Under normal operation, software enables a channel by writing a ‘1’ to the Channel Handler
Enable Register, DMAC_CHER.ENABLE[n], and hardware disables a channel on transfer com-
pletion by clearing the DMAC_CHSR.ENABLE[n] register bit.
The recommended way for software to disable a channel without losing data is to use the SUS-
PEND[n] bit in conjunction with the EMPTY[n] bit in the Channel Handler Status Register.
Channel Enabled by
software
LLI Fetch
Hardware reprograms
SADDRx, CTRLAx,CTRLBx, DSCRx
HDMA buffer transfer
Writeback of control
information of LLI
Is HDMA in
Row 1 ?
Channel Disabled by
hardware
Buffer Complete interrupt
generated here
HDMA Transfer Complete
interrupt generated here
yes
no