Rainbow Electronics AT91CAP9S250A - Manual (Page 212)

212
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
23.2 DDRSDRC Module Diagram
Figure 23-1. DDRSDRC Module Diagram
DDRSDRC is partitioned in two blocks (see Figure 23-1 ):
• An Interconnect-Matrix that manages concurrent accesses on the AHB bus between four
AHB masters and integrates an arbiter.
• A controller that translates AHB requests (Read/Write) in the SDRAM protocol.
Interconnect Matrix
Input
Stage
Input
Stage
Input
Stage
Input
Stage
Output
Stage
Arbiter
Memory Controller
Finite State Machine
SDRAM Signal Management
Addr, DQM
Interface APB
APB
Data
Asynchronous Timing
Refresh Management
DDR-SDR
Devices
Power Management
AHB Slave Interface 0
AHB Slave Interface 1
AHB Slave Interface 2
AHB Slave Interface 3
DQS
DDR-SDR Controller
ras,cas,we
cke
clk/nclk