Rainbow Electronics AT91CAP9S250A - Manual (Page 457)

457
6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
33. Serial Peripheral Interface (SPI)
33.1 Description
The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides
communication with external devices in Master or Slave Mode. It also enables communication
between processors if an external processor is connected to the system.
The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to
other SPIs. During a data transfer, one SPI system acts as the “master”' which controls the
data flow, while the other devices act as “slaves'' which have data shifted into and out by the
master. Different CPUs can take turn being masters (Multiple Master Protocol opposite to Sin-
gle Master Protocol where one CPU is always the master while all of the others are always
slaves) and one master may simultaneously shift data into multiple slaves. However, only one
slave may drive its output to write data back to the master at any given time.
A slave device is selected when the master asserts its NSS signal. If multiple slave devices
exist, the master generates a separate slave select signal for each slave (NPCS).
The SPI system consists of two data lines and two control lines:
• Master Out Slave In (MOSI): This data line supplies the output data from the master shifted
into the input(s) of the slave(s).
• Master In Slave Out (MISO): This data line supplies the output data from a slave to the
input of the master. There may be no more than one slave transmitting data during any
particular transfer.
• Serial Clock (SPCK): This control line is driven by the master and regulates the flow of the
data bits. The master may transmit data at a variety of baud rates; the SPCK line cycles
once for each bit that is transmitted.
• Slave Select (NSS): This control line allows slaves to be turned on and off by hardware.