Rainbow Electronics AT91CAP9S250A - Manual (Page 215)

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6264A–CAP–21-May-07
AT91CAP9S500A/AT91CAP9S250A
11. A Mode Register set (MRS) cycle is issued to program the parameters of the DDR-
SDRAM devices, in particular CAS latency, burst length and to disable DLL reset. The
application must set Mode to 3 in the Mode Register (see
Section 23.6.1 on page 233 )
and perform a write access to the DDR-SDRAM to acknowledge this command. The
write address must be chosen so that BA[1:0] are set to 0. For example, with a 16-bit
128 MB SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write
access should be done at the address 0x20000000
12. A mode Normal command is provided. Program the normal mode into Mode Register
(see Section 23.6.1 on page 233 ). Perform a write access to any DDR-SDRAM address
to acknowledge this command.
13. Perform a write access to any DDR-SDRAM address.
14. Write the refresh rate into the count field in the Refresh Timer register (see page 234 ).
(Refresh rate = delay between refresh cycles). The DDR-SDRAM device requires a
refresh every 15.625 µs or 7.81 µs. With a 100 MHz frequency, the refresh timer timer
count register must to be set with (15.625 /100 MHz) = 1562 i.e. 0x061A or (7.81 /100
MHz) = 781 i.e. 0x030d
After initialization, the DDR-SDRAM devices are fully functional.
23.3.3 Mobile DDR-SDRAM Initialization
The initialization sequence is generated by software. The Mobile DDR-SDRAM devices are ini-
tialized by the following sequence:
1. Program the memory device type into the Configuration Register (see Section 23.6.7
on page 242 ).
2. Program the features of the Mobile DDR-SDRAM device into the Configuration Regis-
ter: asynchronous timing (trc, DDRSDRAMC, etc.), number of columns, rows, banks,
cas latency. See
Section 23.6.3 on page 235 , Section 23.6.4 on page 237 and Section
23.6.5 on page 239 .
3. Program temperature compensated self refresh (tcr), Partial array self refresh (pasr)
and Drive strength (ds) into the Low-power Register. See
Section 23.6.6 on page 240 .
A minimum pause of 200 µs will be provided to precede any signal toggle.
4. An NOP command will be issued to the DDR-SDRAM. Program NOP command into
the Mode Register, the application must set Mode to 1 in the Mode Register (see
Sec-
tion 23.6.1 on page 233 ). Perform a write access to any DDR-SDRAM address to
acknowledge this command. Now clocks which drive DDR-SDRAM device are enabled.
5. An all banks precharge command is issued to the DDR-SDRAM. Program all banks
precharge command into the Mode Register, the application must set Mode to 2 in the
Mode Register (See
Section 23.6.1 on page 233 ). Perform a write access to any DDR-
SDRAM address to acknowledge this command.
6. Two auto-refresh (CBR) cycles are provided. Program the auto refresh command
(CBR) into the Mode Register, the application must set Mode to 4 in the Mode Register
(see
Section 23.6.1 on page 233 ). Perform a write access to any DDR-SDRAM location
twice to acknowledge these commands.
7. An Extended Mode Register set (EMRS) cycle is issued to program the DDR-SDRAM
parameters (TCSR, PASR, DS). The application must set Mode to 5 in the Mode Regis-
ter (see
Section 23.6.1 on page 233 ) and perform a write access to the SDRAM to
acknowledge this command. The write address must be chosen so that BA[1] or BA[0]
are set to 1. For example, with a 16-bit 128 MB SDRAM (12 rows, 9 columns, 4 banks)
bank address, the SDRAM write access should be done at the address 0x20800000 or
0x20400000.