Texas Instruments MSP430x1xx - Manual (Page 83)

Instruction Set Overview
5-19
16-Bit CPU
5.3.2 Single-Operand Instructions
Figure 5–8 illustrates the single-operand instruction format.
Figure 5–8. Single Operand Instruction Format
B/W D/S-Reg
15 0
Opcode
8 7 14 13 12 11 10 9 6 5 4 3 2 1
Ad
Table 5–16 describes the effects of an instruction on the single operand
instruction status bits.
Table 5–16.Single Operand Instruction Format Results
Mnemonic S-Reg, D-Reg Operation Status Bits
V N Z C
RRC dst C –> MSB –>.......LSB –> C * * * *
RRA dst MSB –> MSB –>....LSB –> C 0 * * *
PUSH src SP – 2 –> SP, src –> @ SP – – – –
SWPB dst swap bytes – – – –
CALL dst SP – 2 –> SP – – – –
PC+2 –> stack, dst –> PC
RETI TOS –> SR, SP <– SP + 2 X X X X
TOS –> PC, SP <– SP + 2
SXT dst Bit 7 –> Bit 8........Bit 15 0 * * *
* The status bit is affected
– The status bit is not affected
0 The status bit is cleared
1 The status bit is set
All addressing modes are possible for the CALL instruction. If the symbolic
mode (ADDRESS), the immediate mode (#N), the absolute mode (&EDE) or
the indexed mode X (RN) is used, the word that follows contains the address
information.