Texas Instruments MSP430x1xx - Manual (Page 196)

Timer Modes
11-20
- Interrupt flag CCIFGx, located in control word CCTLx, is set.
- An interrupt is requested if interrupt enable bits CCIEx and GIE are set.
- Signal EQUx is output to the output unit. This signal affects the output
OUTx, depending on the selected output mode.
The EQU0 signal is true when the timer value is greater or equal to the TBCL0
value. The EQU1 to EQUx signals are true when the timer value is equal to the
corresponding TBCL1 to TBCLx values.
11.4.2.1 Capture/Compare Block—Compare Mode—Compare Latch TBCLx
The compare logic uses the data in the compare latch for its comparison with
the timer value. The compare data is first written by software to the capture/
compare register CCRx and then automatically transferred to the compare
latch on a user-selectable load event. The load event is selected with the
CLLDx bits in each CCTLx register.
In addition, the compare latches may be grouped together so that each
compare latch in a group is updated simultaneously on the load event. All
compare latches may be grouped together in a single group, or they may be
grouped in groups of two or three compare latches. The grouping is configured
with the TBCLGRP bits in the TBCTL register. When using groups, the CLLDx
bits of the lowest numbered CCRx register in the group determine the load
event for each compare latch of the group except when all 7 compare latches
are grouped together (TBCLGRP=3). For example, if a user selects the
compare latches to be grouped in groups of three, then there are two groups
of three: TBCL1, TBCL2, and TBCL3 form one group, and TBCL4, TBCL5, and
TBCL6 form the other group. In this scenario, the CLLDx bits for TBCL1 deter-
mine the load event for the first group, and the CLLDx bits for TBCL4 determine
the load event for the second group. The CLLDx bits in CCTL2, CCTL3,
CCTL5, and CCTL6 are unused. When all compare latches are grouped to-
gether (TBCLGRP=3), then the CLLDx bits in TBCL1 determine the load
event.
When using groups, two conditions must exist for the compare latches to be
loaded. First, all CCRx registers of the group must be updated (except when
using immediate mode); second, the load event must occur. This means that
if a user intends to retain any CCRx register data of a group when updating the
group, the old data must be written to the CCRx register again. Otherwise, the
compare latches will not be updated.
The CLLDx bits in the applicable CCTLx register select the load event. There
are four choices for the load event:
- Immediate
- When TBR counts to 0
- Continuous mode or up mode – when TBR counts to 0
Up/down mode – when TBR counts to TBCL0 or counts to 0
- When TBR counts to TBCLx