Texas Instruments MSP430x1xx - Manual (Page 82)

Instruction Set Overview
5-18
5.3.1 Double-Operand Instructions
Figure 5–7 illustrates the double-operand instruction format.
Figure 5–7. Double Operand Instruction Format
B/W D-Reg
15 0
Opcode Ad S-Reg
8 7 14 13 12 11 10 9 6 5 4 3 2 1
As
Table 5–15 describes the effects of an instruction on double operand
instruction status bits.
Table 5–15.Double Operand Instruction Format Results
Mnemonic S-Reg, D-Reg Operation Status Bits
V N Z C
MOV src,dst src –> dst – – – –
ADD src,dst src + dst –> dst * * * *
ADDC src,dst src + dst + C –> dst * * * *
SUB src,dst dst + .not.src + 1 –> dst * * * *
SUBC src,dst dst + .not.src + C –> dst * * * *
CMP src,dst dst – src * * * *
DADD src,dst src + dst + C –> dst (dec) * * * *
AND src,dst src .and. dst –> dst 0 * * *
BIT src,dst src .and. dst 0 * * *
BIC src,dst .not.src .and. dst –> dst – – – –
BIS src,dst src .or. dst –> dst – – – –
XOR src,dst src .xor. dst –> dst * * * *
* The status bit is affected
– The status bit is not affected
0 The status bit is cleared
1 The status bit is set
Note: Instructions CMP and SUB
The instructions CMP and SUB are identical except for the storage of the
result. The same is true for the BIT and AND instructions.