Texas Instruments MSP430x1xx - Manual (Page 152)

Timer Modes
10-12
In up/down mode, the interrupt flags (CCIFG0 and TAIFG) are set at equal time
intervals (Figure 10–15). Each flag is set only once during the period, but they
are separated by 1/2 the timer period. CCIFG0 is set when the timer
counts
from CCR0–1 to CCR0, and TAIFG is set when the timer completes counting
down from 0001h to 0000h. Each flag is capable of producing a CPU interrupt
when enabled.
Figure 10–15. Up/Down Mode Flag Setting
CCR0–1 CCR0 2h 1h 0h 1h
Timer
Clock
Timer
Set
TAIFG
Set
CCIFG0
CCR0–1 CCR0–2
Up/Down
10.3.4.1 Timer In Up/Down Mode—Changing the Value of Period Register CCR0
Changing the period value while the timer is running in up/down mode is even
trickier than in up mode. Like in up mode, the phase of the timer clock when
CCR0 is changed affects the timer’s behavior. Additionally, in up/down mode,
the direction of the timer also affects the behavior.
If the timer is counting in the up direction when the new period is written to
CCR0, the conditions in the up/down mode are identical to those in the up
mode. See Section 10.3.2.1 for details. However, if the timer is counting in the
down direction when CCR0 is updated, it continues its descent until it reaches
zero. The new period takes effect only after the counter finishes counting down
to zero. See Figure 10–16.
Figure 10–16. Altering CCR0—Timer in Up/Down Mode
0 1 2 3 4 5 4 3 2 1 0 1 2 3 4 3 2 1 0 1 2 3 2 1 0 1 2 1 0 1 2 3 4 5 4 3 2 1 0 1 2 1
5 4 2 5 2
5
4
3
2
1
0
Timer
Register
2 CCR0