Texas Instruments MSP430x1xx - Manual (Page 192)

Timer Modes
11-16
11.4.1 Capture/Compare Block—Capture Mode
The capture mode is selected if the mode bit CAPx, located in control word
CCTLx, is set. The capture mode is used to fix time events. It can be used for
speed computations or time measurements. The timer value is copied into the
capture register (CCRx) with the selected edge (positive, negative, or both) of
the input signal. Captures may also be initiated by software as described in
section 11.4.1.1.
If a capture is performed:
- The interrupt flag CCIFGx, located in control word CCTLx, is set.
- An interrupt is requested if both interrupt enable bits CCIEx and GIE are
set.
The input signal to the capture/compare block is selected using control bits
CCISx1 and CCISx0, as shown in Figure 11–18. The input signal can be read
at any time by the software by reading bit CCIx.
Figure 11–18.Capture Logic Input Signal
Capture
Mode
CCISx0 CCISx1
CCIxA
CCIxB
GND
0
1
2
3
V
CC
CCMx1 CCMx0
Set_CCIFGx
0
0
1
1 0
1
0
1 Disabled
Positive Edge
Negative Edge
Both Edges
1
0
CAPx
CCIx
EQUx
CMAx
Synchronize
Capture
Timer
Clock
0
1
Capture
SCSx
The capture signal can also be synchronized with the timer clock to avoid race
conditions between the timer data and the capture signal. This is illustrated in
Figure 11–19. The bit SCSx in capture/compare control register CCTLx
selects the capture signal synchronization.
Figure 11–19.Capture Signal
n-2
Timer
Clock
Timer
Set
CCIFGx
Capture
ÎÎÎ
n+1
CCIx
n-1 n+2 n+3 n+4 n+5 n+6 n