Texas Instruments MSP430x1xx - Manual (Page 415)

Flash Memory Organization
C-3
Flash Memory
bus and memory data bus. When a second module (here Module2) is
implemented, program code in this module can be executed while Module1 is
disconnected.
Figure C–2.Flash Memory Module1 Disabled, Module2 Can Execute Code
Simultaneously
ROM RAM
CPU
Incl. 16 Reg.
Test
JTAG
Flash
Memory
Module 1
MAB, 16 Bit
MDB, 16 Bit
TDI
TDO/TDI
TMS
TCK
Test/VPP
Flash
Memory
Module 2
To Other
Peripheral
Modules
Optional
One MSP430 flash memory module will have, in addition to its code segments,
extra flash memory called
information memory.