Texas Instruments MSP430x1xx - Manual (Page 210)

Timer_B Registers
11-34
Table 11–8. Capture/Compare Control Register Output Mode
Bit
Value
Output Mode Description
0 Output only The OUTx signal reflects the value of the OUTx bit
1 Set EQUx sets OUTx
2 PWM
toggle/reset EQUx toggles OUTx. EQU0 resets OUTx.
3 PWM set/reset EQUx sets OUTx. EQU0 resets OUTx
4 Toggle EQUx toggles OUTx signal.
5 Reset EQUx resets OUTx.
6 PWM
toggle/set EQUx toggles OUTx. EQU0 sets OUTx.
7 PWM reset/set EQUx resets OUTx. EQUx sets OUTx.
Note: OUTx updates with rising edge of timer clock for all modes except mode 0.
Modes 2, 3, 6, 7 not useful for output unit 0.
Bit 8: CAP sets capture or compare mode.
0: Compare mode
1: Capture mode
Bits 9, 10: CLLD: Select load source for compare latch TBCLx
(also see description of bits TBCLGRP, 13 and 14, in TBCTL)
CLLD = 0: Immediate
CLLD = 1: Load CCRx data to TBCLx when TBR counts to 0
CLLD = 2: UP/DOWN mode: load CCRx data to TBCLx when
TBR
counts to TBCL0 or to 0
Continuous mode or UP-mode: load CCRx data
to TBCLx when TBR counts to 0
CLLD = 3: CCRx data are loaded to TBCLx when TBR
counts
to TBCLx
Bit 11: SCSx bit:
This bit is used to synchronize the capture input signal with the
timer clock.
0: asynchronous capture
1: synchronous capture
Bits 12, 13: Input select, CCIS0 and CCIS1:
These two bits define the capture signal source. These bits are
not used in compare mode.
0
Input CCIxA is selected
1 Input CCIxB is selected
2 GND
3 V
CC
Bits 14, 15: Capture mode bits:
Table 11–8 describes the capture mode selections.