Texas Instruments MSP430x1xx - Manual (Page 255)

Interrupt and Control Functions
13-9
USART Peripheral Interface, SPI Mode
13.4 Interrupt and Control Functions
The USART peripheral interface serves two main interrupt sources for
transmission and reception. Two interrupt vectors serve receive and transmit
interrupt events.
The interrupt control bits and flags and enable bits of the USART peripheral
interface are located in the SFR address range. The bit functions are
described below in Table 13–1. See the peripheral-file map in Appendix A for
the exact bit locations.
Table 13–1.USART Interrupt Control and Enable Bits—SPI Mode
Receive interrupt flag URXIFG Initial state reset (by PUC/SWRST)
Receive interrupt enable URXIE Initial state reset (by PUC/SWRST)
Receive/transmit enable
(see Note) USPIE Initial state reset (by PUC)
Transmit interrupt flag UTXIFG Initial state set (by PUC/SWRST)
Transmit interrupt enable UTXIE Initial state reset (by PUC/SWRST)
Note: Different for UART mode, see Chapter 12.
The USART receiver and transmitter operate in parallel and use the same
baud-rate generator in synchronous master mode. In synchronous slave
mode, the external clock applied to UCLK is used for the receiver and the
transmitter. The receiver and transmitter are enabled and disabled together
with the USPIE bit.
13.4.1 USART Receive/Transmit Enable Bit, Receive Operation
The receive/transmit enable bit (USPIE) enables or disables collection of the
bit stream on the URXD/SOMI data line. Disabling the USART receiver
(USPIE = 0) stops the receive operation after completion, or stops a pending
operation if no receive operation is active. In synchronous mode, UCLK does
not shift any data into the receiver shift register.
13.4.1.1 Receive/Transmit Enable Bit—MSP430 as Master
The receive operation functions identically for three-pin and four-pin modes,
as shown in Figure 13–7, when the MSP430 USART is selected to be the SPI
master.