Texas Instruments MSP430x1xx - Manual (Page 51)

Operating Modes
3-21
System Resets, Interrupts, and Operating Modes
The following example describes clearing low-power mode 0.
;===Interrupt service routine=================================
...... ;CPU is active while handling interrupts
BIC #10h,0(SP) ;Clears the CPUOff bit in the SR contents
;that were stored on the stack.
RETI ;RETI restores the CPU to the active state
;because the SR values that are stored on
;the stack were manipulated. This occurs
;because the SR is pushed onto the stack
;upon an interrupt, then restored from the
;stack after the RETI instruction.
3.5.2 Low - Power Modes 2 and 3 (LPM2 and LPM3)
Low-power mode 2 or 3 is selected if bits CPUOff and SCG1 in the status
register are set. Immediately after the bits are set, CPU, MCLK, and SMCLK
operations halt and all internal bus activities stop until an interrupt request or
reset occurs.
Peripherals that operate with the MCLK or SMCLK signal are inactive because
the clock signals are inactive. Peripherals that operate with the ACLK signal
are active or inactive according with the individual control registers and the
module enable bits in the SFRs. All I/O port pins and the RAM/registers are
unchanged. Wake up is possible by enabled interrupts coming from active
peripherals or RST/NMI.
3.5.3 Low - Power Mode 4 (LPM4)
In low power mode 4 all activities cease; only the RAM contents, I/O ports, and
registers are maintained. Wake up is only possible by enabled external
interrupts.
Before activating LPM4, the software should consider the system conditions
during the low power mode period . The two most important conditions are
environmental (that is, temperature effect on the DCO), and the clocked
operation conditions.
The environment defines whether the value of the frequency integrator should
be held or corrected. A correction should be made when ambient conditions
are anticipated to change drastically enough to increase or decrease the
system frequency while the device is in LPM4.