Texas Instruments MSP430x1xx - Manual (Page 62)

RAM and Peripheral Organization
4-10
Table 4–2. Peripheral File Address Map—Byte Modules
Address Description
00F0h – 00FFh Reserved
00E0h – 00EFh Reserved
00D0h – 00DFh Reserved
00C0h – 00CFh Reserved
00B0h – 00BFh Reserved
00A0h – 00AFh Reserved
0090h – 009Fh Reserved
0080h – 008Fh ADC12 memory control
0070h – 007Fh USART0, USART1
0060h – 006Fh Reserved
0050h – 005Fh System clock generator, Comparator A
0040h – 004Fh Reserved
0030h – 003Fh Digital I/O port P5, digital I/O port P6
0020h – 002Fh Digital I/O port P1 and P2 control
0010h – 001Fh Digital I/O port P3, and P4 control
0000h – 000Fh Special function
4.4.3 Peripheral Modules-Special Function Registers (SFRs)
The system configuration and the individual reaction of the peripheral modules
to the processor operation is configured in the SFRs as described in
Table 4–3. The SFRs are located in the lower address range, and are
organized by bytes. SFRs must be accessed using byte instructions only.