Texas Instruments MSP430x1xx - Manual (Page 213)

Timer_B Registers
11-37
Timer_B
Table 11–10. Vector Register TBIV Description
Interrupt
Priority
Interrupt Source Short Form
Vector Register
TBIV Contents
Highest † Capture/compare 1 CCIFG1 2
Capture/compare 2 CCIFG2 4
Capture/compare 3 ‡ CCIFG3 6
Capture/compare 4 ‡ CCIFG4 8
Capture/compare 5 ‡ CCIFG5 10
Capture/compare 6 ‡ CCIFG6 12
Lowest Timer overflow TBIFG 14
No interrupt pending 0
† Highest pending interrupt other than CCIFG0. CCIFG0 is always the highest priority Timer_B
interrupt.
‡ 14x devices only
Accessing the TBIV register automatically resets the highest pending interrupt
flag. If another interrupt flag is set, then another interrupt will be immediately
generated after servicing the initial interrupt. For example, if both CCIFG2 and
CCIFG3 are set, when the interrupt service routine accesses the TBIV register
(either by reading it or by adding it directly to the PC), CCIFG2 will be reset
automatically. After the RETI instruction of the interrupt service routine is
executed, the CCIFG3 flag will generate another interrupt.
Note: Writing to Read-Only Register TBIV
Register TBIV should not be written to. If a write operation to TBIV is
performed, the interrupt flag of the highest-pending interrupt is reset.
Therefore, the requesting interrupt event is missed. Additionally, writing to
this read-only register results in increased current consumption as long as
the write operation is active.