Texas Instruments MSP430x1xx - Manual (Page 425)

Flash Memory Control Registers
C-13
Flash Memory
- The supply voltage should be within the devices’ electrical conditions and
can only vary slightly, as specified in the applicable data sheet
The control bit BUSY indicates that the write or segment-write cycle is active.
It is set by the instruction that writes data to the flash memory module and
starts the timing generator. It remains set until the write cycle is completed and
the programming voltage is removed. In the write mode the BUSY bit indicates
if the flash memory is ready for another write operation. In segment write mode
the WAIT bit indicates if the flash memory is ready for another write operation
and the BUSY bit indicates the segment write operation is completed. In case
of emergency, the emergency exit bit EMEX is set and stops the write cycle
immediately. The programming voltage is switched off. One situation where
the write cycle should be stopped by software is when the supply voltage drops
drastically and the controller’s operating conditions may be exceeded. Anoth-
er case is when the flash memory timing gets out of control, as when the clock-
source signal is lost.
Note:
Whenever the write cycle is stopped before its normal ending by the hard-
ware, the timing generator is stopped and the data written in flash memory
may be marginal. Data reading may be inconsistently valid when varying the
supply voltage, the temperature, the access time (instruction execution, data
read), or the time.
C.3 Flash Memory Control Registers
Defining the correct control bits of three control registers enables write (pro-
gram), erase, or mass-erase. All three registers should be accessed using
word instructions only. The control registers are protected against false write
or erase cycles via a key word. Any violation of this keyword sets the KEYV
bit and requests a nonmaskable interrupt (NMI). The keyword is different to the
keyword used with the Watchdog Timer.
All control bits are reset during PUC. PUC is activated after V
CC
is applied, a
reset condition is applied to the RST/NMI pin or watchdog, or a flash operation
was not performed normally.
C.3.1 Flash Memory Control Register FCTL1
Any write to control register FCTL1 during erase, mass-erase, or write (pro-
gramming) will end in an access violation with ACCVIFG=1. In an active seg-
ment-write mode, the control register can be written if wait mode is active
(WAIT=1). In an active segment write mode and while WAIT=0, writing to con-
trol register FCTL1 will also end in an access violation with ACCVIFG=1.
Read access is possible at any time without restrictions.
Any write to control register FCTL1 during erase, mass-erase, or write (pro-
gramming) will end in an access violation with ACCVIFG=1. In an active seg-