Texas Instruments MSP430x1xx - Manual (Page 235)

Control and Status Registers
12-19
USART Peripheral Interface, UART Mode
RXWake is reset by accessing the receive buffer (URXBUF), by
a USART software reset, or by a system-reset PUC signal.
Bit 2: The receive wake-up interrupt-enable bit (URXWIE) selects the
type of character to set the interrupt flag (URXIFG):
URXWIE = 0: Each character received sets the URXIFG
URXWIE = 1: Only characters that are marked as address
characters set the interrupt flag URXIFG. It
operates identically in both multiprocessor
modes.
The wake-up interrupt enable feature depends on the receive
erroneous-character feature. See also Bit 3, URXEIE.
Bit 3: The receive erroneous-character interrupt-enable bit URXEIE
selects whether an erroneous character is to set the interrupt
flag URXIFG.
URXEIE = 0: Each erroneous character received does not
alter the interrupt flag URXIFG.
URXEIE = 1: All characters can set the interrupt flag URXIFG
as described in Table 12–4, depending on the
conditions set by the URXWIE bit.
Table 12–4.Interrupt Flag Set Conditions
URXEIE URXWIE
Char.
w/Error
Char.
Address
Description Flag URXIFG
After a Character is Received
0 X 1 X Unchanged
0 0 0 X Set
0 1 0 0 Unchanged
0 1 0 1 Set
1 0 X X Set (Receives all characters)
1 1 X 0 Unchanged
1 1 X 1 Set
Bit 4: The break detect bit (BRK) is set when a break condition occurs
and the URXEIE bit is set. The break condition is recognized if
the RXD line remains continuously low for at least 10 bits,
beginning after a missing first stop bit. It is not cleared by receipt
of a character after the break is detected, but is reset by a
SWRST, a system reset, or by reading the URXBUF. The receive
interrupt flag URXIFG is set if a break is detected.
Bit 5: The overrun error flag bit OE is set when a character is
transferred into the URXBUF before the previous character is
read out. The previous character is overwritten and lost. OE is
reset by a SWRST, a system reset, or by reading the URXBUF.
Bit 6: The parity error flag bit PE is set when a character is received
with a mismatch between the number of 1s and its parity bit, and
is loaded into the receive buffer. The parity checker includes the
address bit, used in the address-bit multiprocessor mode, in the