Texas Instruments MSP430x1xx - Manual (Page 178)

Introduction
11-2
11.1 Introduction
Timer_B is an extremely versatile timer made up of :
- 16-bit counter with 4 operating modes and four selectable lengths (8-bit,
10-bit, 12-bit, or 16-bit)
- Selectable and configurable clock source
- Up to seven independently-configurable capture/compare registers with
configurable inputs and double-buffered compare registers.
- Up to seven individually-configurable output modules with eight output
modes
Timer_B can support multiple, simultaneous, timings; multiple capture/
compares; multiple output waveforms such as PWM signals; and any com-
bination of these. In addition, with the double-buffering of compare data, multi-
ple PWM periods can be updated simultaneously.
Additionally, Timer_B has extensive interrupt capabilities. Interrupts may be
generated from the counter on overflow conditions and from each of the cap-
ture/compare registers on captures or compares. Each capture/compare
block is individually configurable and can produce interrupts on compares or
on rising, falling or both edges of an external capture signal.
The block diagram of Timer_B is shown in Figure 11–1.
11.1.1 Similarities and Differences From Timer_A
Timer_B is almost identical to Timer_A (except for a few enhancements noted
below) and operates identically to Timer_A in it’s default condition.
Timer_B is different from Timer_A in the following ways:
1) The length of Timer_B is programmable to be 8, 10, 12, or 16 bits, where-
as Timer_A is only a 16-bit timer.
2) The SCCI bit functionality of the capture/compare registers of Timer_A is
not implemented in Timer_B.
3) The function of the capture/compare registers for the compare mode of
Timer_B has changed slightly.
4) On some devices a pin is implemented to put all Timer_B outputs into a
high-impedance state. Check the device data sheet for the presence of
this pin.
On Timer_A, the capture/compare register CCRx holds the data for the
comparison to the timer value. On Timer_B, each CCRx acts as a buffer for
a compare latch, and the compare latch holds the data used for the
comparison. So, compare data is written to each CCRx in both timers;
however, in Timer_B, the compare data is then transferred to the compare
latch for the comparison. The timing of the transfer of the compare data from