Texas Instruments MSP430x1xx - Manual (Page 206)

Timer_B Registers
11-30
Bit 2: Timer clear (CLR) bit. The timer and input divider are reset with the
POR signal, or if bit CLR is set. The CLR bit is automatically reset
and is always read as zero. The timer starts in the upward direction
with the next valid clock edge, unless halted by cleared mode
control bits.
Bit 3: Not used
Bits 4, 5: Mode control: Table 11–5 describes the mode control bits.
Table 11–5. Mode Control
MC1 MC0 Count Mode Description
0 0 Stop Timer is halted.
0 1 Up to CCR0 Timer counts up to TBCL0 and restarts at 0.
Note: If TBCL0 > TBR
(max),
the counter counts to
zero with the next rising edge of timer clock.
1 0 Continuous up Timer counts up to TBR
(max)
and restarts at 0.
The maximum value of TBR [TBR
(max)
] is:
0FFFFh for 16-bit configuration
00FFFh for 12-bit configuration
003FFh for 10-bit configuration
000FFh for 8-bit configuration
1 1 Up/down Timer continuously counts up to CCR0 and back
down to 0.
Note: If CCR0 > TBR
(max),
the counter operates
as if it were configured for continuous mode. It
will not count down from TBR
(max)
to zero.
Bits 6, 7: Input divider control bits. Table 11–6 describes the clock-divider
bits.
Table 11–6. Input Clock Divider Control Bits
ID1 ID0 Operation Description
0 0 /1 Input clock source is passed to the timer.
0 1 /2 Input clock source is divided by two.
1 0 /4 Input clock source is divided by four.
1 1 /8 Input clock source is divided by eight.
Bits 8, 9: Clock source selection bits. Table 11–7 describes the clock source
selections.
Table 11–7. Clock Source Selection
SSEL1 SSEL0 O/P Signal Comment
0 0 TBCLK See data sheet device description
0 1 ACLK Auxiliary clock ACLK is used
1 0 SMCLK System clock SMCLK
1 1 INCLK See device description in data sheet