Texas Instruments MSP430x1xx - Manual (Page 233)

Control and Status Registers
12-17
USART Peripheral Interface, UART Mode
CHAR = 0: 7-bit data
CHAR = 1: 8-bit data
Bit 5: Number of stop bits
This bit determines the number of stop bits transmitted. The
receiver checks for one stop bit only.
SP = 0: one stop bit
SP = 1: two stop bits
Bit 6: Parity odd/even
If the PENA bit is set (parity bit is enabled), the PEV bit defines
odd or even parity according to the number of odd or even 1 bits
(in both the transmitted and received characters), the address
bit (address-bit multiprocessor mode), and the parity bit.
PEV = 0: odd parity
PEV = 1: even parity
Bit 7: Parity enable
If parity is disabled, no parity bit is generated during
transmission or expected during reception. A received parity bit
is not transferred to the URXBUF with the received data as it is
not considered one of the data bits. In address-bit multi-
processor mode, the address bit is included in the parity
calculation.
PEN = 0: Parity disable
PEN = 1: Parity enable
Note: Mark and Space Definitions
The mark condition is identical to the signal level in the idle state. Space is
the opposite signal level: the start bit is always space.
12.5.2 Transmit Control Register UTCTL
The transmit control register (UTCTL), shown in Figure 12–17, controls the
USART hardware associated with the transmit operation.
Figure 12–17. Transmitter Control Register UTCTL
7 0
rw–0
UTCTL1, 07Bh
SSEL1 CKPL SSEL0 TXEPT URXSE
rw–0 rw–0 rw–0 rw–0 rw–0 rw–1
Unused TXWake
rw–0
Unused
UTCTL0, 071h
Bit 0: The transmitter empty (TXEPT) flag is set when the transmitter
shift register and UTXBUF are empty, and is reset when data is
written to UTXBUF. It is set by a SWRST.
Bit 1: Unused
Bit 2: The TXWake bit controls the transmit features of the
multiprocessor communication modes. Each transmission
—started by loading the UTXBUF—uses the state of the
TXWake bit to initialize the address-identification feature. It must
not be cleared—the USART hardware clears this bit once it is
transferred to the WUT; a SWRST also clears the TXWake bit.