Texas Instruments MSP430x1xx - Manual (Page 172)

Timer_A Registers
10-32
JMP TIMMOD1 ; Vector 2: Module 1 2
JMP TIMMOD2 ; Vector 4: Module 2 2
JMP TIMMOD3 ; Vector 6: Module 3 2
JMP TIMMOD4 ; Vector 8: Module 4 2
;
; Module 5. Timer Overflow Handler: the Timer Register is
; expanded into the RAM location TIMEXT (MSBs)
;
TIMOVH
; Vector 10: TIMOV Flag
INC TIMEXT ; Handle Timer Overflow 4
RETI 5
;
TIMMOD2
; Vector 4: Module 2
ADD #NN,&CCR2 ; Add time difference 5
... ; Task starts here
RETI ; Back to main program 5
;
;
TIMMOD1
; Vector 2: Module 1
ADD #MM,&CCR1 ; Add time difference 5
... ; Task starts here
RETI ; Back to main program 5
; If all five CCR registers are not implemented on a
; device, the interrupt vectors for the register that are
; present must still be handled.
TIMMOD4
RETI ; Simply return 5
; The Module 3 handler shows a way to look if any other
; interrupt is pending: 5 cycles have to be spent, but
; 9 cycles may be saved if another interrupt is pending
;
TIMMOD3
; Vector 6: Module 3
ADD #PP,&CCR3 ; Add time difference 5
... ; Task starts here
JMP TIM_HND ; Look for pending interrupts 2
;
.SECT ”VECTORS”,0FFF0h ; Interrupt Vectors
; The vector address may be different for different
; devices.
;
.WORD TIM_HND ; Vector for Capture/Compare
; Module 1..4 and timer overflow
; TAIFG
.WORD TIMMOD0 ; Vector for Capture/Compare
; Module 0
If the CPU clock MCLK was turned off (CPUOFF=1), then two or three
additional cycles need to be added for synchronous start of the CPU. The delta
of one clock cycle is caused when clocks are asynchronous to the restart of
CPU clock MCLK.
The software overhead for different interrupt sources includes interrupt
latency and return-from-interrupt cycles (but not the task handling itself), as
described:
- Capture/compare block CCR0 11 cycles
- Capture/compare blocks CCR1 to CCR4 16 cycles
- Timer overflow TAIFG 14 cycles