Texas Instruments MSP430x1xx - Manual (Page 147)

Timer Modes
10-7
Timer_A
10.3 Timer Modes
10.3.1 Timer—Stop Mode
Stopping and starting the timer is done simply by changing the mode control
bits (MCx). The value of the timer is not affected.
When the timer is stopped from up/down mode and then restarted in up/down
mode, the timer counts in the same direction as it was counting before it was
stopped. For example, if the timer is in up/down mode and counting in the down
direction when the MCx bits are reset, when they are set back to the up/down
direction, the timer starts counting in the down direction from its previous
value. If this is not desired in an application, the CLR bit in the TACTL register
can be used to clear this direction memory feature.
10.3.2 Timer—Up Mode
The up mode is used if the timer period must be different from the 65,536
(16-bit) clock cycles of the continuous mode period. The capture/compare
register CCR0 data define the timer period.
The counter counts up to the content of compare register CCR0, as shown in
Figure 10–5. When the timer value and the value of compare register CCR0
are equal (or if the timer value is greater than the CCR0 value), the timer
restarts counting from zero.
Figure 10–5. Timer Up Mode
0FFFFh
0h
CCR0
Flag CCIFG0 is set when the timer equals the CCR0 value. The TAIFG flag is
set when the timer
counts from CCR0 to zero. All interrupt flags are set
independently of the corresponding interrupt enable bit, but an interrupt is
requested only if the corresponding interrupt enable bit and the GIE bit are set.
Figure 10–6 shows the flag set cycle.
Figure 10–6. Up Mode Flag Setting
CCR0–1 CCR0 0h 1h CCR0–1 CCR0 0h 1h
Timer
Clock
Timer
Set Flag
TAIFG
Set Flag
CCIFG0