Texas Instruments MSP430x1xx - Manual (Page 171)

Timer_A Registers
10-31
Timer_A
Table 10–9.Vector Register TAIV Description
Interrupt
Priority
Interrupt Source Short Form
Vector Register
TAIV Contents
Highest † Capture/compare 1 CCIFG1 2
Capture/compare 2 CCIFG2 4
Capture/compare 3 ‡ CCIFG3 6
Capture/compare 4 ‡ CCIFG4 8
Timer overflow TAIFG 10
Reserved 12
Lowest Reserved 14
No interrupt pending 0
† Highest pending interrupt other than CCIFG0. CCIFG0 is always the highest priority Timer_A
interrupt.
‡ 14x devices only
Accessing the TAIV register automatically resets the highest pending interrupt
flag. If another interrupt flag is set, then another interrupt will be immediately
generated after servicing the initial interrupt. For example, if both CCIFG2 and
CCIFG3 are set, when the interrupt service routine accesses the TAIV register
(either by reading it or by adding it directly to the PC), CCIFG2 will be reset
automatically. After the RETI instruction of the interrupt service routine is
executed, the CCIFG3 flag will generate another interrupt.
Note: Writing to Read-Only Register TAIV
Register TAIV should not be written to. If a write operation to TAIV is
performed, the interrupt flag of the highest-pending interrupt is reset.
Therefore, the requesting interrupt event is missed. Additionally, writing to
this read-only register results in increased current consumption as long as
the write operation is active.
10.6.4.3 Timer Interrupt Vector Register, Software Example
The following software example describes the use of vector word TAIV and the
handling overhead. The numbers at the right margin show the necessary
cycles for every instruction. The example is written for continuous mode: the
time difference to the next interrupt is added to the corresponding compare
register.
; Software example for the interrupt part Cycles
;
; Interrupt handler for Capture/Compare Module 0.
; The interrupt flag CCIFG0 is reset automatically
;
TIMMOD0
... ; Start of handler Interrupt latency 6
RETI 5
;
; Interrupt handler for Capture/Compare Modules 1 to 4.
; The interrupt flags CCIFGx and TAIFG are reset by
; hardware. Only the flag with the highest priority
; responsible for the interrupt vector word is reset.
TIM_HND
$ ; Interrupt latency 6
ADD &TAIV,PC ; Add offset to Jump table 3
RETI ; Vector 0: No interrupt 5