Texas Instruments MSP430x1xx - Manual (Page 146)

Timer_A Operation
10-6
10.2.3 Starting the Timer
The timer may be started or restarted in a variety of ways:
- Release Halt Mode: The timer counts in the selected direction when a tim-
er mode other than stop mode is selected with the MCx bits.
- Halted by CCR0 = 0, restarted by CCR0 > 0 when the mode is either up
or up/down: When the timer mode is selected to be either up or up/down,
the timer may be stopped by writing 0 to capture/compare register 0
(CCR0). The timer may then be restarted by writing a nonzero value to
CCR0. In this scenario, the timer starts incrementing in the up direction
from zero.
- Setting the CLR bit in TACTL register: Setting the CLR bit in the TACTL
register clears the timer value and input clock divider value. The timer in-
crements upward from zero with the next clock cycle as long as stop-mode
is not selected with the MCx bits.
- TAR is loaded with 0: When the counter (TAR register) is loaded with zero
with a software instruction the timer increments upward from zero with the
next clock cycle as long as stop-mode is not selected with the MCx bits.