Texas Instruments MSP430x1xx - Manual (Page 227)

Interrupt and Enable Functions
12-11
USART Peripheral Interface, UART Mode
12.4 Interrupt and Enable Functions
The USART peripheral interface serves two main interrupt sources for
transmission and reception. Two interrupt vectors serve receive and transmit
events.
The interrupt control bits and flags and enable bits of the USART peripheral
interface are located in the SFR registers. They are discussed in Table 12–1.
See the peripheral file map in Appendix A for the exact bit locations.
Table 12–1.USART Interrupt Control and Enable Bits – UART Mode
Receive interrupt flag URXIFG Initial state reset (by PUC/SWRST)
Receive interrupt enable URXIE Initial state reset (by PUC/SWRST)
Receive enable (see note) URXE Initial state reset (by PUC)
Transmit interrupt flag UTXIFG Initial state set (by PUC/SWRST)
Transmit interrupt enable UTXIE Initial state reset (by PUC/SWRST)
Transmit enable.(see note) UTXE Initial state reset (by PUC)
Note: Different for SPI mode, see Chapter 13.
The USART receiver and transmitter operate independently, but use the same
baud rate.
12.4.1 USART Receive Enable Bit
The receive enable bit URXE, shown in Figure 12–12, enables or disables
receipt of the bit stream on the URXD data line. Disabling the USART receiver
stops the receive operation after completion of receiving the character, or
stops immediately if no receive operation is active. Start-bit detection is also
disabled.
Figure 12–12. State Diagram of Receiver Enable
Idle State
(Receiver
Enabled)
Receive
Disable
Receiver
Collects
Character
URXE = 0
No Valid Start Bit
Not Completed
URXE = 1
URXE = 0
URXE = 1
Valid Start Bit
Handle Interrupt
Conditions
Character
Received
URXE = 1
URXE = 0
Note: URXE Reenabled, UART Mode
Because the receiver is completely disabled, reenabling the receiver is
asynchronous to any data stream on the communication line.
Synchronization can be performed by looking for an idle line condition before
receiving a character.